basic_64x.asm

本源代码为TI 公司TMS320C6416 DSP芯片自检测程序

;/****************************************************************************\
; *           Copyright (C) 2000 Texas Instruments Incorporated.             *
; *                           All Rights Reserved                            *
; *                                                                          *
; * GENERAL DISCLAIMER                                                       *
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; * All software and related documentation is provided "AS IS" and without   *
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; * all other warranties, express or implied, including, but not limited to, *
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; * purpose.  Under no circumstances shall Texas Instruments be liable for   *
; * any incidental, special or consequential damages that result from the    *
; * use or inability to use the software or related documentation, even if   *
; * Texas Instruments has been advised of the liability.                     *
;\****************************************************************************/

;This routine checks load and Store operations. 

		.ref _Inst_Test     ;system initialization section
		.ref main_shell ;the main control shell that calls 
				;all the subroutines
		.def basic



		.sect   "basichk"
		.copy "BBU_DD_CoreOption.h"
		.global _CSR1

;ARGUMENTS PASSED TO THIS ROUTINE
;A4 = 0FFFFh
;B4 = 5454h 
;A6 = 5151h
;B6 = 3333h
;A8 = AAAAh
;B8 = 2222h
;A10 = FFFFFFFFh
;B10 = 00000003h

basic:

;saving (or pushing) appropriate registers onto the stack

		STW     .D2     A10, *B15--[1]  ;decrementing SP
		STW     .D2     B10, *B15--[1]  ;coping variables
		STW     .D2     B11, *B15--[1]  ;A0-A9, B0-B9 are 

;****************************************************
;* checking all load instructions (LDB, LDH, LDW)   *
;* A value is loaded from memory by using a pointer *
;* which was defined and initialized in CHK6x.ASM   *
;* as follows:                                      *
;*              MVK     .S1     a, A1               *
;*              MVKH    .S1     a, A1               *
;*                                                  *
;* A1 points to a (memory space) and contains its   *
;* address. In this routine, we check whether a     *
;* value has indeed been loaded to register B0.     *
;****************************************************
		
		LDW     .D1     *A1, B0         ;**checking basic load was *A1
		NOP     4                       ;whether B0 is loaded
		SUB     .L2x    B0, A4, B0      ;B0 = 0, if B0 = A4
	[B0]    B       .S1     ERRBASIC1       ;ERROR, if B0 != 0
		NOP     5                       

;ADVANCED LOAD INSTRUCTIONS AND TESTS
		.if (.LITTLE_ENDIAN)				; LITTLE ENDIAN
		LDW     .D1     *+A1[2], A5     ;**load word (A5 = A6)
		NOP 4
		LDHU    .D1     *+A1[4], B5     ;**load halfword = 5151h
		NOP 4
		LDBU    .D1     *+A1[8], B7     ;**load byte B7 = 51h
		NOP     4                       ;2/4/8 all pt to same 
		CMPEQ   .L2x    B5, A5, B0      ;B0 = 1, if B5 = A5
		SUB     .L2     B0, 1, B0       ;B0 = 0
	[B0]    B       .S1     ERRBASIC1       ;ERROR, if B0 != 0
		NOP     5

		CMPGT   .L2     B5, B7, B0      ;LDH or LDW will always
		SUB     .L2     B0, 1, B0       ;be greater than LDB
	[B0]    B       .S2     ERRBASIC1       ;B0 = 0, if not-> ERROR
		NOP     5

;LDH and LDB with sign extension (default)
		LDW     .D1     *+A1[0], A5     ;**A5 = 0000FFFFh
		NOP 4
		LDH     .D1     *+A1[0], B5     ;**B5 = FFFFFFFFh(sig ex)
		NOP 4
		LDB     .D1     *+A1[0], B7     ;**B7 = FFFFFFFFh(sig ex)
		NOP     4
		CMPEQ   .L2     B5, A10, B1     ;B1 = 1, B5 = A10
		CMPEQ   .L2     B7, A10, B2     ;B2 = 1, B7 = A10
		SUB     .L2     B1, B2, B1      ;B1 = 0, B1 = B2
	[B1]    B       .S2     ERRBASIC1       ;ERROR, if B1 != 0
		NOP     5
		.endif
		
		.if (.BIG_ENDIAN)				;BIG ENDIAN
		LDW     .D1     *+A1[2], A5     ;**load word (A5 = A6)
		NOP 4
		LDHU    .D1     *+A1[5], B5     ;**load halfword = 5151h
		NOP 4
		LDBU    .D1     *+A1[10], B7     ;**load byte B7 = 51h
		NOP     4                       ;2/4/8 all pt to same 
		CMPEQ   .L2x    B5, A5, B0      ;B0 = 1, if B5 = A5
		SUB     .L2     B0, 1, B0       ;B0 = 0
	[B0]    B       .S1     ERRBASIC1       ;ERROR, if B0 != 0
		NOP     5

		CMPGT   .L2     B5, B7, B0      ;LDH or LDW will always
		SUB     .L2     B0, 1, B0       ;be greater than LDB
	[B0]    B       .S2     ERRBASIC1       ;B0 = 0, if not-> ERROR
		NOP     5

;LDH and LDB with sign extension (default)
		LDW     .D1     *+A1[0], A5     ;**A5 = 0000FFFFh
		NOP 4
		LDH     .D1     *+A1[1], B5     ;**B5 = FFFFFFFFh(sig ex)
		NOP 4
		LDB     .D1     *+A1[2], B7     ;**B7 = FFFFFFFFh(sig ex)
		NOP     4
		CMPEQ   .L2     B5, A10, B1     ;B1 = 1, B5 = A10
		CMPEQ   .L2     B7, A10, B2     ;B2 = 1, B7 = A10
		SUB     .L2     B1, B2, B1      ;B1 = 0, B1 = B2
	[B1]    B       .S2     ERRBASIC1       ;ERROR, if B1 != 0
		NOP     5
		.endif
		
;********************************************************
;* The following section checks all store instructions  *
;* (STB, STH, STW). A value is the stored from a regis. *
;* into a memory location and then loading it back from *
;* it to do a compare it with a known argument or result*
;********************************************************
		STW     .D1     A6, *+A1[8]     ;storing A6 into mem.
		LDW     .D1     *+A1[8], B9     ;loading it back to B9
		NOP     4                       ;will check if A6 = B9
		SUB     .L2x    A6, B9, B0      ;B0 = 0, if A6 = B9
	[B0]    B       .S2     ERRBASIC2       ;ERROR, if B0 != 0
		NOP     5

		STH     .D1     A6, *+A1[8]     ;storing 16bits of A6
		LDH     .D1     *+A1[8], B9     ;loading it back to B9
		NOP     4                       ;will check if A6 = B9
		CMPEQ   .L2x    A6, B9, B0      ;B0 = 1, if A6 = B9
		SUB     .L2     B0, 1, B0       ;B0 = 0
	[B0]    B       .S2     ERRBASIC2       ;ERROR, if B0 != 0
		NOP     5

		STB     .D1     A6, *+A1[8]     ;storing 8bits of A6
		LDB     .D1     *+A1[8], B9     ;loading it back to B9
		NOP     4                       ;A6 = 5151h, B9 = 51h
		CMPGT   .L2x    A6, B9, B1      ;B1 = 1, if A6 > B9
		SUB     .L2     B1, 1, B1       ;B1 = 0
	[B1]    B       .S2     ERRBASIC2       ;ERROR, if B1 != 0
		NOP     5
				
;*************************************************
;* This segment of the test routine tests the MV *
;* instruction to move data from one register to *
;* another. It also tests the MVC instruction    *
;* which is used to write or read from control   *
;* status registers. e.g. CSR, AMR, IRP          *
;*************************************************
		MV      .S1     A4, A9          ;A4 -> A9, same side
		MV      .S2x    A4, B9          ;A4 -> B9, B side
		CMPEQ   .L2x    A9, B9, B1      ;B1 = 1, A9 = B9
		SUB     .L2     B1, 1, B1       ;B1 = 0
	[B1]    B       .S2     ERRBASIC3       ;ERROR, if B1 != 0
		NOP     5                       

;writing to and reading from control status register
		MVC     .S2     A8, AMR         ;writing to AMR
		MVC     .S2     AMR, B9         ;reading from AMR
		SUB     .L2x    A8, B9, B1      ;B1 = 0, if A8 = B9
	[B1]    B       .S1     ERRBASIC3       ;ERROR, if B1 != 0
		MVC     .S2     B1, AMR         ;ZEROing AMR
		NOP     4                       ;1/5 delays used by 
						;a useful instruction
;CSR control register

		MVKL     .S1    _CSR1, A2  		;Expected Result 6416 LE=0x08010103 BE=0x08010003 
										; 00030103h EXPECTED RESULT for C6203 //phm
										;EXPECTED RESULT for C6416 //djh
										;EXPECTED RESULT for Big En 	0x0C010003
										;EXPECTED RESULT for Little En 	0x0C010103
		MVKH    .S1     _CSR1, A2   
		LDW     .D1	*A2,A2
		NOP 4
		OR 		.L1		A2,B10,A2	
		

		MVC     .S2     CSR, B11        ;reading CSR into B11
		MVC     .S2     B10, CSR        ;writing B10 to CSR
		MVC     .S2     CSR, B9         ;reading from CSR = B9
		SUB     .L1x    A2, B9, A2      ;A2 = 0, if A2 = B9
	[A2]    B       .S1     ERRBASIC3       ;ERROR, if A2 != 0
		MVC     .S2     B11, CSR        ;refreshing the value
		NOP     4

;IRP control register
		MVC     .S2     IRP, B2         ;reading IRP to B1
		MVC     .S2     B6, IRP         ;writing B10 to IRP
		MVC     .S2     IRP, B9         ;reading IRP into B1
		CMPEQ   .L2     B9, B6, B1      ;B1 = 1, if B9 = B10
		SUB     .L2     B1, 1, B1       ;B1 = 0
	[B1]    B       .S1     ERRBASIC3       ;ERROR, if B1 != 0
		MVC     .S2     B2, IRP         ;refresh org. value
		NOP     3

;NRP control register
		MVC     .S2     NRP, B2         ;reading NRP to B1
		MVC     .S2     B4, NRP         ;writing B10 to NRP
		MVC     .S2     NRP, B9         ;reading NRP into B1
		CMPEQ   .L2     B9, B4, B1      ;B1 = 1, if B9 = B10
		SUB     .L2     B1, 1, B1       ;B1 = 0
	[B1]    B       .S1     ERRBASIC3       ;ERROR, if B1 != 0
		MVC     .S2     B2, NRP         ;refresh org. value
		NOP     3

;************************************************
;* This segment of the routine checks the ZERO  *
;* instruction. This instruction clears a       *
;* register or, in other words, zeros it out    *
;************************************************
		MV      .S2x    A4, B1
		ZERO    .L2     B1 
	[B1]    B       .S1     ERRBASIC4
		NOP     5

;*************************************************
;* The following part checks MVK, MVKH and MVKLH *
;* instructions. It starts with simple constant  *
;* (lower 16bits) to a register and then higher  *
;* 16bits to a register.                         *
;*************************************************
		MV      .S2x    A4, B2          ;B2 = 0000FFFFh
		MVKL     .S2     0h, B2
	[B2]    B       .S1     ERRBASIC5
		NOP     5

		MV      .S2x    A10, B2         ;B2 = FFFFFFFFh         
		MVKH    .S2     0h, B2          ;B2 = 0000FFFFh
		CMPEQ   .L2x    B2, A4, B2      ;B2 = 1, if B2 = A4
		SUB     .L2     B2, 1, B2       ;B2 = 0
	[B2]    B       .S1     ERRBASIC5       ;ERROR, if B2 != 0
		NOP     5

;testing MVKLH (A10 = FFFFFFFFh, A4 = 0000FFFFh)
		MV      .S1     A4, A5          ;A5 = 0000FFFFh
		MVKLH   .S1     0FFFFh, A5      ;A5 = FFFFFFFFh
		CMPEQ   .L1     A5, A10, A2     ;A2 = 1, if A5 = A10            
		SUB     .L1     A2, 1, A2       ;A2 = 0
	[A2]    B       .S1     ERRBASIC5       ;ERROR, if A2 != 0
		NOP     5

;loading (or popping) appropriate registers from the stack
ENDBASIC:
		LDW     .D2     *++B15[1], B11  ;responsible for 
		LDW     .D2     *++B15[1], B10  ;before returning to
		LDW     .D2     *++B15[1], A10  ;the calling routine
		NOP     4

		B       .S2     B3      ;RETURN TO THE 
		NOP     5               ;MAIN CONTROL SHELL


;*
;* ERROR HANDLERS
;*

ERRBASIC1:      MVKL     .S2     11h, B0         ;LOAD FAIL CODE
		B       .S2     ENDBASIC        ;LDW, LDH(U), LDB(U)
		NOP     5

ERRBASIC2:      MVKL     .S2     12h, B0         ;STORE FAIL CODE
		B       .S2     ENDBASIC        ;STW, STH, STB
		NOP     5

ERRBASIC3:      MVKL     .S2     13h, B0         ;MV, MVC FAIL CODE
		B       .S2     ENDBASIC
		NOP     5

ERRBASIC4:      MVKL     .S2     14h, B0         ;ZERO Fail code
		B       .S2     ENDBASIC
		NOP     5

ERRBASIC5:      MVKL     .S2     15h, B0         ;MVK, MVKH, MVKLH
		B       .S2     ENDBASIC        ;FAIL CODE
		NOP     5