📄 sat_64x.asm
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;/****************************************************************************\
; * Copyright (C) 2000 Texas Instruments Incorporated. *
; * All Rights Reserved *
; * *
; * GENERAL DISCLAIMER *
; * ------------------ *
; * All software and related documentation is provided "AS IS" and without *
; * warranty or support of any kind and Texas Instruments expressly disclaims*
; * all other warranties, express or implied, including, but not limited to, *
; * the implied warranties of merchantability and fitness for a particular *
; * purpose. Under no circumstances shall Texas Instruments be liable for *
; * any incidental, special or consequential damages that result from the *
; * use or inability to use the software or related documentation, even if *
; * Texas Instruments has been advised of the liability. *
;\****************************************************************************/
;This test checks the saturation instructions
.ref _Inst_Test ;system initialization section
.ref main_shell ;the main control shell that calls
;all the subroutines
.def sat
;************************************************************
;* *
;* SATURATION INSTRUCTIONS TEST *
;* *
;* This routine checks operations dealing with *
;* saturation. *
;* *
;* Written by Syed A. Maroof *
;* ATS/DSP Applications *
;* Texas Instruments Inc. *
;* *
;* Release Version 1.1 *
;* Last Update: 05/08/98 *
;* Modified Code Update: 09/24/01 *
;* Reason: instruction-set extended for 64x *
;* Modified by Douglas Harrington *
;* Wireless Infrastructure * *
;************************************************************
.sect "satchk"
.global _CSR2
; .copy "BBU_DD_CoreOption.h"
;ARGUMENTS PASSED TO THIS ROUTINE
;A4 = 0FFFFh
;B4 = 5454h
;A6 = 5151h
;B6 = 3333h
;A8 = AAAAh
;B8 = 2222h
;A10 = FFFFFFFFh
;B10 = 00000003h
sat:
;saving (or pushing) appropriate registers onto the stack
STW .D2 A10, *B15--[1] ;decrementing SP
STW .D2 B10, *B15--[1] ;coping variables
STW .D2 B11, *B15--[1] ;onto the stack
;checking all instructions involving saturation
SSHL .S2x A8, 16, B9 ;B9 = 7FFFFFFFh
;****************************************************************
; if the result is > or equal to 80000000h, SSHL saturates it *
; to 7FFFFFFFh and writes the sat. bit in CSR control register. *
; CSR = 00010300h *
;****************************************************************
MVKL .S1 _CSR2, A7 ;
MVKH .S1 _CSR2, A7 ;
LDW .D1 *A7,A7
NOP 4
MVKL .S1 0xF3FEFFFF, A12 ;code used to MASK out sat bit because sometimes PGIE or GIE bits
MVKH .S1 0xF3FEFFFF, A12 ;get set which cause test to fail this way we only check sat bit
AND .L1 A7, A12, A12
SHR .S1 A12, 9, A12
MVC .S2 CSR, B7 ;READ FROM CSR
MVKL .S2 0xF3FEFFFF, B12
MVKH .S2 0xF3FEFFFF, B12
AND .L2 B7, B12, B12
SHR .S2 B12, 9 , B12
CMPEQ .L1x A12, B12, A2 ;A2 = 1, if B7 = A7
SUB .L1 A2, 1, A2 ;A2 = 0
[A2] B .S1 ERRSAT1 ;ERROR, if A2 != 0
CLR .S2 B7, 9, 9, B7 ;Clearing CSR
MVC .S2 B7, CSR ;WRITING TO CSR
NOP 3 ;CSR = 00010100h
ZERO .L1 A12 ;put A12 back to zero
ZERO .L2 B12 ;put B12 back to zero
;***************************************************************
; ADD will give a value greater than 7FFFFFFFh while SADD will *
; saturate it to 7FFFFFFFh *
;***************************************************************
;A7 = 00010300h for this segment as well - EXPECTED RESULT
SHL .S1 A6, 16, A9 ;A7 = 51510000h
OR .L2x A9, B4, B2 ;B2 = 51515454h
ADD .S2x A9, B2, B1 ;B1 = A2A25454h
SADD .L1x A9, B2, A2 ;A2 = 7fffffffh
CMPGTU .L2x B1, A2, B1 ;B1 = 00000001h
SUB .L2 B1, 1, B1 ;B1 = 0
[B1] B .S2 ERRSAT2 ;ERROR, if B1 != 0
NOP 2 ;3/5 delay slots are
;filled w/ useful
;instructions.
MVC .S2 CSR, B7 ;READ FROM CSR
;code used to mask of one bit
SHR .S1 A7, 4, A7
SHR .S2 B7, 4, B7
CMPEQ .L1x A7, B7, A2 ;A2 = 1, if B7 = A7
SUB .L1 A2, 1, A2 ;A2 = 0
[A2] B .S1 ERRSAT2 ;ERROR, if A2 != 0
;changing back to correct CSR
MVKL .S1 _CSR2, A7
MVKH .S1 _CSR2, A7
MVKL .S2 _CSR2, B7
MVKH .S2 _CSR2, B7
LDW .D1 *A7,A7
LDW .D2 *B7,B7
NOP 4
CLR .S2 B7, 9, 9, B7 ;Clearing CSR for next
;changing back to correct CSR
MVC .S2 B7, CSR ;WRITING TO CSR
NOP 3 ;CSR = 00010100h
;2/5 delay slots are
;filled w/ useful
;instructions
;saturating a 40-bit value to a 32-bit value
;A7 = 00010300h again representing EXPECTED RESULT
MVK .S2 11h, B11 ;B11 = 00000011h
SAT .L2 B11:B10, B9 ;B9 = 7FFFFFFFh
ZERO .L2 B11 ;B11 = 0h
MVC .S2 CSR, B7 ;READING FROM CSR
CMPEQ .L1x A7, B7, A2 ;A2 = 1, if B7 = A7
SUB .L1 A2, 1, A2 ;A2 = 0
[A2] B .S1 ERRSAT3 ;ERROR, if A2 != 0
;NOTE: Instead of NOP 5, the branch delay slots can be filled with
;useful instructions like in this particular code segment.
CLR .S2 B7, 9, 9, B7 ;CLEARING 9th bit of B7
MVC .S2 B7, CSR ;WRITING TO CSR
SAT .L2 B11:B10, B9 ;SHOULD NOT SATURATE
ZERO .L2 B2 ;B2 = 0h
MVC .S2 CSR, B7 ;CSR -> B7
CMPGTU .L2x A7, B7, B2 ;B2 = 1, if A7 > B7
SUB .L2 B2, 1, B2 ;B2 = 0
[B2] B .S1 ERRSAT3 ;ERROR, if B2 != 0
NOP 5
;subtraction using saturation
;A7 = 00010300h - EXPECTED RESULT for CSR
MVKL .S1 80000003h, A9 ;A9 = 00000003h
MVKH .S1 80000003h, A9 ;A9 = 80000003h
SSUB .L2x B10, A9, B9 ;B9 = 7FFFFFFFh
SUB .L2x A10, B10, B11 ;B11 = FFFFFFFCh
MVC .S2 CSR, B7 ;CSR -> B7
CMPEQ .L1x A7, B7, A2 ;A2 = 1, if B7 = A7
SUB .L1 A2, 1, A2 ;A2 = 0
[A2] B .S1 ERRSAT4 ;ERROR, if A2 != 0
CMPGTU .L2 B11, B9, B2 ;B2 = 1, if B11 > B9
SUB .L2 B2, 1, B2 ;B2 = 0
NOP 3
[B2] B .S2 ERRSAT4 ;ERROR, if B2 != 0
CLR .S2 B7, 9, 9, B7 ;CLEARING 9th bit of B7
MVC .S2 B7, CSR ;B7 -> CSR
NOP 3 ;CSR = 00010100h
;checking for SMPY(L)(H) instruction
;A7 = 00010300h - EXPECTED VALUE in CSR
MVKL .S1 80008000h, A5 ;A5 = 00008000h
MVKH .S1 80008000h, A5 ;A5 = 80008000h
MV .L2x A5, B5 ;B5 = 80008000h
SMPY .M2x A5, B5, B11 ;B11 = 7FFFFFFFh
NOP 2 ;SATURATES
MVC .S2 CSR, B7 ;CSR -> B7
CMPEQ .L1x A7, B7, A2 ;A2 = 1, if B7 = A7
SUB .L1 A2, 1, A2 ;A2 = 0
[A2] B .S1 ERRSAT5 ;ERROR, if A2 != 0
CLR .S2 B7, 9, 9, B7 ;CLEARING 9th bit of B7
MVC .S2 B7, CSR ;B7 -> CSR
NOP 3 ;CSR = 00010100h
SMPYHL .M1x A5, B5, A2 ;A2 = 7FFFFFFFh
NOP 2 ;SATURATES
MVC .S2 CSR, B7 ;CSR -> B7
CMPEQ .L1x A7, B7, A2 ;A2 = 1, if B7 = A7
SUB .L1 A2, 1, A2 ;A2 = 0
[A2] B .S1 ERRSAT5 ;ERROR, if A2 != 0
CLR .S2 B7, 9, 9, B7 ;CLEARING 9th bit of B7
MVC .S2 B7, CSR ;B7 -> CSR
NOP 3 ;CSR = 00010100h
SMPYLH .M2x A5, B5, B11 ;B11 = 7FFFFFFFh
NOP 2 ;SATURATES
MVC .S2 CSR, B7 ;CSR -> B7
CMPEQ .L1x A7, B7, A2 ;A2 = 1, if B7 = A7
SUB .L1 A2, 1, A2 ;A2 = 0
[A2] B .S1 ERRSAT5 ;ERROR, if A2 != 0
CLR .S2 B7, 9, 9, B7 ;CLEARING 9th bit of B7
MVC .S2 B7, CSR ;B7 -> CSR
NOP 3 ;CSR = 00010100h
;checking for non-saturated result
MVKL .S1 008A0000h, A5 ;A5 = 00000000h
MVKH .S1 008A0000h, A5 ;A5 = 008A0000h
MVK .S2 00A7h, B5 ;B5 = 000000A7h
SMPYHL .M2 A5, B5, B2 ;B2 = 0000B40Ch
NOP 2 ;NO SATURATION
CLR .S1 A7, 9, 9, A7 ;A7 = 00010100h
MVC .S2 CSR, B7 ;CSR -> B7
CMPEQ .L2x A7, B7, B2 ;B2 = 1, if B7 = A7
SUB .L2 B2, 1, B2 ;B2 = 0
[B2] B .S2 ERRSAT6 ;ERROR, if B2 != 0
NOP 5
;*************************************************************************
;Code for instruction-set exteded for C64x support *
;checking for instruction ABS2 *
;*************************************************************************
;checking instruction SADD2
;Add with Saturation, Signed Packed 16-bit
MVKL .S2 0x5789F23A, B16 ;B16 = src1
MVKH .S2 0x5789F23A, B16 ;B16 = src1
MVKL .S2 0x74B84975, B18 ;B18 = src2
MVKH .S2 0x74B84975, B18 ;B18 = src2
MVKL .S2 0x7FFF3BAF, B19 ;B19 = result
MVKH .S2 0x7FFF3BAF, B19 ;B19 = result
SADD2 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRSAT7 ;ERROR, if B0 !=0
NOP 5
;checking instruction SADDU4
;Add with Saturation, Unsigned Packed 8-bit
MVKL .S2 0xCBFFFFAF, B19 ;B19 = result
MVKH .S2 0xCBFFFFAF, B19 ;B19 = result
SADDU4 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRSAT8 ;ERROR, if B0 !=0
NOP 5
;checking instruction SADDUS2
;Add with Saturation, Unsigned Packed 8-bit
MVKL .S2 0xCC41FFFF, B19 ;B19 = result
MVKH .S2 0xCC41FFFF, B19 ;B19 = result
SADDUS2 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRSAT9 ;ERROR, if B0 !=0
NOP 5
;checking instruction SADDSU2
;Add with Saturation, Unsigned Packed 8-bit
MVKL .S2 0xCC413BAF, B19 ;B19 = result
MVKH .S2 0xCC413BAF, B19 ;B19 = result
SADDSU2 .S2 B16, B18, B20
CMPEQ .L2 B19, B20, B0 ;B0 = 1
[!B0] B .S1 ERRSAT10 ;ERROR, if B0 !=0
NOP 5
;Since all my branches for errors are taken for [!B0] I need to
;set B0 equal to 0 so I dont get an overall error for Alu_6461
MVKL .S2 0x00000000, B0
;loading (or popping) appropriate registers from the stack
ENDSAT:
LDW .D2 *++B15[1], B11 ;loading app. values
LDW .D2 *++B15[1], B10 ;before returning to
LDW .D2 *++B15[1], A10 ;the calling routine
NOP 4
B .S2 B3 ;RETURN TO THE
NOP 5 ;MAIN CONTROL SHELL
;*
;* ERROR HANDLERS
;*
ERRSAT1: MVKL .S2 51h, B0 ;SSHL error
B .S2 ENDSAT
NOP 5
ERRSAT2: MVKL .S2 52h, B0 ;SADD error
B .S2 ENDSAT
NOP 5
ERRSAT3: MVKL .S2 53h, B0 ;SAT error
B .S2 ENDSAT
NOP 5
ERRSAT4: MVKL .S2 54h, B0 ;SSUB error
B .S2 ENDSAT
NOP 5
ERRSAT5: MVKL .S2 55h, B0 ;SMPY(L)(H) error
B .S2 ENDSAT
NOP 5
ERRSAT6: MVK .S2 56h, B0 ;SMPYHL error
B .S2 ENDSAT
NOP 5
ERRSAT7: MVKL .S2 0x0009F04F, B0
MVKH .S2 0x0009F04F, B0 ;SADD2 error
B .S2 ENDSAT
NOP 5
ERRSAT8: MVKL .S2 0x0009F050, B0 ;SADDU4 error
MVKH .S2 0x0009F050, B0
B .S2 ENDSAT
NOP 5
ERRSAT9: MVKL .S2 0x0009F051, B0 ;SADDUS2 error
MVKH .S2 0x0009F051, B0
B .S2 ENDSAT
NOP 5
ERRSAT10: MVKL .S2 0x0009F052, B0 ;SADDSU2 error
MVKH .S2 0x0009F052, B0
B .S2 ENDSAT
NOP 5
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