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📄 f2s.vhd

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---------------------------------------------------------------------------------------------------
--
-- Title       : F2S
-- Design      : gateway
-- Author      : zlm
-- Company     : buaa
--
---------------------------------------------------------------------------------------------------
--
-- File        : P2S.vhd
-- Generated   : Tue Dec 14 23:23:20 2004
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description : 
--
---------------------------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {P2S} architecture {P2S}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


entity F2S is
	 port(
		 clk : in STD_LOGIC;
		 reset : in STD_LOGIC;
		 is_empty : in STD_LOGIC;
		 din : in STD_LOGIC_VECTOR(3 downto 0);
		 rd:out STD_LOGIC;
		 dout_1 : out STD_LOGIC;
		 dout_2 : out STD_LOGIC;
		 dout_3 : out STD_LOGIC;
		 dout_4 : out STD_LOGIC
	     );
end F2S;

--}} End of automatically maintained section

architecture F2S of F2S is

constant framecode:std_logic_vector(7 downto 0):="11110110";
constant idlecode:std_logic_vector(3 downto 0):="0000";

signal reg:std_logic_vector(3 downto 0);

begin

process(clk,reset) 

variable i:integer range 0 to 7;
variable b_cnt:integer range 0 to 255;

begin
	if  reset='1' then
		reg<=idlecode;	  
		i:=0; 
		b_cnt:=0;
		rd<='1';
		dout_1<=idlecode(3);
		dout_2<=idlecode(2);
		dout_3<=idlecode(1);
		dout_4<=idlecode(0);
	elsif clk'event and clk='1'	then
		if b_cnt<=7 then 
			if i=7 then
				dout_1<=framecode(i); 
				dout_2<=framecode(i);
				dout_3<=framecode(i);
				dout_4<=framecode(i);
				i:=0;  
				b_cnt:=b_cnt+1;
				rd<='0';
			else
				dout_1<=framecode(i);
				dout_2<=framecode(i);
				dout_3<=framecode(i);
				dout_4<=framecode(i);
				i:=i+1;
				b_cnt:=b_cnt+1;
			end if; 
		else 
			if b_cnt=255 then
				b_cnt:=0; 
				rd<='1';
			else
				b_cnt:=b_cnt+1;	 
			end if;
			
			if is_empty='0' then
				reg<=din;
				dout_1<=reg(3);
				dout_2<=reg(2);
				dout_3<=reg(1);
				dout_4<=reg(0);
			else
				reg<=idlecode;
				dout_1<=reg(3);
				dout_2<=reg(2);
				dout_3<=reg(1);
				dout_4<=reg(0);
			end if;
			
		end if;			
    end if;		
end process;	


end F2S;

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