fifo2.vhd

以太网到电信网转换的网关（简易版）

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--
-- Title       : fifo2
-- Design      : gateway
-- Author      : zlm
-- Company     : buaa
--
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--
-- File        : fifo2.vhd
-- Generated   : Tue Dec 14 15:44:02 2004
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {fifo2} architecture {fifo2}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


entity fifo2 is	 
	 port(
		 clk_w : in STD_LOGIC;
		 clk_r : in STD_LOGIC;
		 reset : in STD_LOGIC;
		 wr : in STD_LOGIC;
		 rd : in STD_LOGIC;
		 din : in STD_LOGIC;
		 full : out STD_LOGIC;
		 empty : out STD_LOGIC;
		 dout : out STD_LOGIC
	     );
end fifo2;

--}} End of automatically maintained section

architecture fifo2 of fifo2 is

constant w:integer:=1024;

type memory is array(0 to w-1) of std_logic;
signal ram:memory;
signal wp,rp:integer range 0 to w-1;
signal in_full,in_empty:std_logic;

signal cnt:std_logic_vector(6 downto 0);
begin  

full<=in_full;
empty<=in_empty;
dout<=ram(rp);

--write data--
process(clk_w)
begin
	if (clk_w'event and clk_w='1')then
		if (wr='0' and in_full='0')then
			ram(wp)<=din;
		end if;
	end if;
end process;

--change wp--
process(clk_w,reset)
begin
	if (reset='1')then
		wp<=0;
	elsif (clk_w'event and clk_w='1')then
		if (wr='0' and in_full='0')then
			if(wp=w-1)then
				wp<=0;
			else
				wp<=wp+1;
			end if;
		end if;
	end if;	
end process;

--change rp--
process(clk_r,reset)
begin
	if (reset='1')then
		rp<=w-1;
	elsif (clk_r'event and clk_r='1')then
		if (rd='0' and in_empty='0')then
			if(rp=w-1)then
				rp<=0;
			else
				rp<=rp+1;
			end if;
		end if;
	end if;	
end process;
		
--generate empty--
process(clk_r,reset)
begin
	if (reset='1')then
		in_empty<='1';
		cnt<="0000001";
	elsif (clk_r'event and clk_r='1')then 
		if cnt=0 then
			if (rp=wp-2 or (rp=w-1 and wp=1) or (rp=w-2 and wp=0)) then
				in_empty<='1';
				cnt<=cnt+'1';
			elsif (in_empty='1')then
				in_empty<='0';
			end if;
		elsif cnt=127 then
			cnt<=(others=>'0');
		else
			cnt<=cnt+'1';
		end if;	
	end if;	
end process;
	
--generate full--
process(clk_w,reset)
begin
	if (reset='1')then
		in_full<='0';
	elsif (clk_w'event and clk_w='1')then
		if (rp=wp and (rd='1'and wr='0'))then
			in_full<='1';
		elsif (in_full='1'and rd='0')then
			in_full<='0';
		end if;
	end if;	
end process;   


end fifo2;