📄 s2f.vhd
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--
-- Title : S2F
-- Design : gateway
-- Author : zlm
-- Company : buaa
--
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--
-- File : S2F.vhd
-- Generated : Wed Dec 15 19:44:43 2004
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
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--
-- Description :
--
---------------------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {S2F} architecture {S2F}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity S2F is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
din1 : in STD_LOGIC;
din2 : in STD_LOGIC;
din3 : in STD_LOGIC;
din4 : in STD_LOGIC;
is_empty : in STD_LOGIC_VECTOR(3 downto 0);
enable : out STD_LOGIC;
rd : out STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end S2F;
--}} End of automatically maintained section
architecture S2F of S2F is
constant idlecode:std_logic_vector(3 downto 0):="0000";
signal reg:std_logic_vector(3 downto 0);
signal flag:std_logic;
signal flag2:std_logic;
begin
process(clk,reset)
begin
if reset='1'then
enable<='0';
rd<="1111";
dout<=(others=>'0');
reg<=idlecode;
flag<='0';
flag2<='0';
elsif clk'event and clk='1'then
if is_empty="0000" then
rd<="0000";
flag<='1';
else
rd<="1111";
flag<='0';
end if;
if flag='1'then
flag2<='1';
dout<=reg;
reg(3)<=din1;
reg(2)<=din2;
reg(1)<=din3;
reg(0)<=din4;
else
flag2<='0';
dout<=reg;
reg<=idlecode;
end if;
if flag2='1'then
enable<='1';
else
enable<='0';
end if;
end if;
end process;
end S2F;
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