add4.vhd

c#设计模式WithCla

-- This VHDL Source Have been create with WITHCLASS95
-- Scrip file written by Clerbois M

use  WORK.WCLASSPKG.ALL; -- Definition 

package ADDER4PKG is
    COMPONENT ADDER4
	PORT (
--      CLOCK,RESET:IN BIT; only for synchronous object
  A :  IN BV4 ;
  B :  IN BV4 ;
  S :  OUT BV4 ;
  Cout :  OUT BIT  );
	END COMPONENT;
END ADDER4PKG;

use  WORK.WCLASSPKG.ALL; -- Definition 

ENTITY  ADDER4 is 
	PORT (
--      CLOCK,RESET:IN BIT; only for synchronous object
   A :  IN BV4 ;
   B :  IN BV4 ;
   S :  OUT BV4 ;
   Cout :  OUT BIT  );
END ADDER4;

use  WORK.WCLASSPKG.ALL; -- Definition 
use WORK.FullAdderPKG.ALL ;


ARCHITECTURE FSMADDER4 OF ADDER4 IS
 
 SIGNAL SS : BV4;
 SIGNAL CY : BIT_VECTOR(0 TO 4);

BEGIN
--Insert NOT State machine Process here
-- process 

-- AGGREGATION of MANY TO MANY == instantation of objects
-- copy the lines N times and modify the parameters
-- ADD : FullAdder PORT MAP( -- list of signals ) ; 
-- or use or loop
CY(0) <= ZERO;
L1:FOR I in 0 to 3 GENERATE
 	ADD_N : FullAdder PORT MAP(A(I),B(I),CY(I),SS(I),CY(I+1)) ; 
	end generate;


-- AGGREGATION of ONE TO ONE == instantation of an object
-- Generate the instantiation line and modify the parameters


Copy:PROCESS 
begin
  S(0) <= SS(0);
  S(1) <= SS(1);
  S(2) <= SS(2);
  S(3) <= SS(3);
  COUT <= CY(3);
  
end PROCESS Copy;


-- begin
-- end process;

-- Insert here the process source file generated with state code report (cut and paste)
-- Use the script file vhdlst.sct to generate the state machine

END FSMADDER4;