fulladd.vhd

c#设计模式WithCla

-- This VHDL Source Have been create with WITHCLASS95
-- Scrip file written by Clerbois M

use  WORK.WCLASSPKG.ALL; -- Definition 

package FullAdderPKG is
    COMPONENT FullAdder
	PORT (
--      CLOCK,RESET:IN BIT; only for synchronous object
  A :  IN BIT ;
  B :  IN BIT ;
  Cin :  IN BIT ;
  S :  OUT BIT ;
  Cout :  OUT BIT  );
	END COMPONENT;
END FullAdderPKG;

use  WORK.WCLASSPKG.ALL; -- Definition 

ENTITY  FullAdder is 
	PORT (
--      CLOCK,RESET:IN BIT; only for synchronous object
   A :  IN BIT ;
   B :  IN BIT ;
   Cin :  IN BIT ;
   S :  OUT BIT ;
   Cout :  OUT BIT  );
END FullAdder;

use  WORK.WCLASSPKG.ALL; -- Definition 



ARCHITECTURE FSMFullAdder OF FullAdder IS
 
 SIGNAL V : BIT;

BEGIN
--Insert NOT State machine Process here
-- process 

-- AGGREGATION of MANY TO MANY == instantation of objects
-- copy the lines N times and modify the parameters


-- AGGREGATION of ONE TO ONE == instantation of an object
-- Generate the instantiation line and modify the parameters


P1:PROCESS (A,B,CIN)
begin
  V <= A XOR B;
  S <= V XOR CIN;
  COUT <= (A AND B) OR (V AND CIN);
  
end PROCESS P1;


-- begin
-- end process;

-- Insert here the process source file generated with state code report (cut and paste)
-- Use the script file vhdlst.sct to generate the state machine

END FSMFullAdder;