ir.c

ESS 公司VCD软件关于IR的编程！

	tmp = killIR ? 1 : 0;
    }
#else
    if (IS_IRXOR_HIGH) {
	CLEAR_IRXOR;		/* set to low */
	falling_edge = 1; 	/* Interupt caused by IR falling edge */
	/* If we want to kill IR, then send 1; else send 0 */
	tmp = killIR ? 1 : 0;
    } else {
	SET_IRXOR;
	/* If we want to kill IR, then send 0; else send 1 */
	tmp = killIR ? 0 : 1;
    }
#endif

    mvd[riface_clear_dbgirq] = 0;	/* Clear debug_irq	*/

#if (IR_NEC || IR_SANYO)
    IR_core_NEC(falling_edge);
#endif /* IR_NEC || IR_SAYNO */

#ifdef IR_PHILIPS
    IR_core_Philips(falling_edge);
#endif /* IR_PHILIPS */
}

#endif /* else of EAUX_IR */
#endif /* else of DSC_IRQ */
#endif /* IR */

/************************************************************************
  Functions:
*************************************************************************/
void IR_init()
{

    CPRINTF(("IR_init ...\n"));
#ifdef NETWORK
	set_boot_nic();				//read boot nic information
#endif

#ifdef SANYOINT
	extern void EAUX_init_HIRQB(int on, int edge);
	EAUX_init_HIRQB(1, 1); /*enable. falling edge*/
#endif SANYOINT

#ifdef IR
    ir_init();
#endif  

#ifdef HSCOMM
    HSCOMM_init();
#endif
  
}
#ifdef NETWORK
static void WIFI_ExtIRQ_interrupt_service(uint sys_status)
{
    extern int shadow_eaux_irq_ctl;
    int utemp = sys_status;

    if((shadow_eaux_irq_ctl & 0x01) && (utemp & 0x04)) {
	if(utemp & 0x80) mvd[eaux_sys_status] = 0x80;
	mvd[eaux_sys_status] = 0x04;
	mvd[riface_clear_dbgirq] = 0x0;
	IR_recv_interrupt_service(utemp);
    }
#ifdef WILDCAT
    if ((shadow_eaux_irq_ctl & 0x04) &&(utemp & 0x10)) {    
	/*eaux2[5] */
	SET_EAUX4_1;
	mvd[eaux_sys_status] = 0x10;
	mvd[riface_clear_dbgirq] = 0x0;
	if (ETHERNET) {
	    extern int lan_dma_flag;
#ifdef HOSTCTL
	    Hermes_ISR();
#else
	    if(lan_dma_flag) orinoco_ISR_dma();
	    else orinoco_ISR();
	    CLEAR_EAUX4_1;
#endif
	}
    }
#else	//non-wildcat board
    if(((shadow_eaux_irq_ctl & 0x08) && (utemp & 0x20))) {
	SET_EAUX3_2;
	mvd[eaux_sys_status] = 0x20;
	mvd[riface_clear_dbgirq] = 0x0;
	
	if (ETHERNET){
#ifdef HOSTCTL
	    Hermes_ISR();
#else
	    extern int lan_dma_flag;
	    if(lan_dma_flag) orinoco_ISR_dma();
	    else orinoco_ISR();
	    CLEAR_EAUX3_2;
#endif
	}
    }
#endif
    return;
}
#endif

#if defined(BD_BAHAMAS) && defined(DVD_MODEM)
static void EauxIRQ_DVDModem_interrupt_serice(uint sys_status)
{
    extern int shadow_eaux_irq_ctl;
    unsigned int utemp;
  
    utemp = sys_status;

    if ( (utemp & 0x20) && (shadow_eaux_irq_ctl & 0x8) ) { /*aux4 C2PO*/
	mvd[eaux_sys_status] = 0x20;
	IR_recv_interrupt_service(utemp);
    }
#if 0
    if (utemp & 0x80) { 
	mvd[eaux_sys_status] = 0x80;	/* clear overflow here */
    }
    if ( (utemp & 0x8) /*&& (shadow_eaux_irq_ctl & 0x2)*/ ) {/*aux6 S0S1*/
	mvd[eaux_sys_status] = 0x8;
    }
    if ( (utemp & 0x4) /*&& (shadow_eaux_irq_ctl & 0x1)*/ ) {/*aux7 IR*/
	mvd[eaux_sys_status] = 0x4;
    }
#endif
    if ( (utemp & 0x10) && (shadow_eaux_irq_ctl & 0x4) ) {/*aux5 Serial Port*/
	int interupt_enabled = 0;
	int savepsw, irqmask_save;
	mvd[eaux_sys_status] = 0x10;
#if 1
	if (!interupt_enabled) {
	    interupt_enabled = 1;
	    savepsw = get_sr();
	    irqmask_save = mvd[riface_irqmask];
	    set_sr(0x1fc3);
	    mvd[riface_irqmask] = RIFACE_LD_IRQSUPRESS | vout_irq |debug_irq;
	}
#endif
	
#if 1
	if (!in_ide_dma){
	    if (modem_init_finish) DSPinterrupt();
	}
	else {
	    DebugService ++;
	    if (DebugService>=2) { 
		EPRINTF(("miss dbg %d, %d, %d, %d \n",
			 DebugService,in_ide_dma,
			 in_ide_cmd_service,ide_cmd_state));
	    }
	}
#endif
#if 1
	if (interupt_enabled) {
	    mvd[riface_irqmask] = irqmask_save;
	    set_sr(savepsw);
	}
#endif
    }
}
#endif


#ifdef EAUX_IR
static void EauxIRQ_IR_interrupt_service(uint sys_status)
{
    extern int shadow_eaux_irq_ctl;
    unsigned int utemp;
    
    utemp = sys_status;
#ifdef SPECIAL_AUX_IR	
    if (utemp & 0x80)  
	mvd[eaux_sys_status] = 0x80;	/* clear overflow here */
	
    IR_recv_interrupt_service(utemp);
#else
    if(EAUX2_7_LOW){
	if (utemp & 0x80) { 
	    mvd[eaux_sys_status] = 0x80;	/* clear overflow here */
#ifdef IR_NEC
		wrongIRwidth = 0;
#endif
	}
	IR_recv_interrupt_service(utemp);
    } else {	
	/* somehow the rising edge also trigger the interrupt */
#ifdef IR_NEC		
	wrongIRwidth = (mvd[eaux_ir_diff] & 0xff) + 1;
#endif
    }	
#endif /* SPECIAL_AUX_IR */
}
#endif

#if EAUX_ENABLE_S0S1 
static void EauxIRQ_S0S1_interrupt_service(void)
{  
    /*eaux2[6] */
#if defined BHLDR && defined CDG
    extern void DCI_subcode_frame_irs (void);
    DCI_subcode_frame_irs(); 
#endif
}
#endif

#ifdef EAUX_ENABLE_16550
static void EauxIRQ_SP_interrupt_service(void)
{
#if defined(UART550)
    UART_interrupt_service();
#endif 
}
#endif

#ifdef EAUX_ENABLE_C2PO
static void EauxIRQ_C2PO_interrupt_service(void)
{
	extern unsigned int shadow_eaux_irq_ctl;
#ifdef NETWORK //for wildcat LAN code
    extern int lan_dma_flag;
#endif    
    
#ifdef NETWORK //for wildcat LAN code
    mvd[eaux_sys_status] = 0x20;
#ifdef HOSTCTL
    DISABLE_C2PO;
    SMC_ISR();
#else
    if(lan_dma_flag) LanISR_dma();
    else LanISR();
#endif /* HOSTCTL */

#else /* ETHER_NET */
    C2PO_interrupt = 1;              
#endif /* ETHER_NET */

}
#endif /*ENABLE_C2PO */

#ifdef EAUX_IRQ
static void EauxIRQ_interrupt_service(void)
{
    extern int shadow_eaux_irq_ctl;
    unsigned int utemp;

    utemp = mvd[eaux_sys_status] & 0xff;
    mvd[eaux_sys_status] = utemp & 0x3D;	/*clear the interrupt here */
    mvd[riface_clear_dbgirq] = 0;

#if defined(BD_BAHAMAS) && defined(DVD_MODEM)
    EauxIRQ_DVDModem_interrupt_service(utemp);
    return;
#endif
    /*Not DVD_MODEM*/
#if defined(EAUX_IR)   
    if ((shadow_eaux_irq_ctl & IR_IRQ_MASK) 
	&& (utemp & SYS_IR_IRQ)){
	EauxIRQ_IR_interrupt_service(utemp);
    }
#endif /*EAUX_IR */
       

#ifdef EAUX_ENABLE_S0S1
    if ((shadow_eaux_irq_ctl &  S0S1_IRQ_MASK)
	&&(utemp & SYS_S0S1_IRQ)) { 
	/*eaux2[6] */
	EauxIRQ_S0S1_interrupt_service();
    }
#endif

#ifdef EAUX_ENABLE_C2PO
    if ((shadow_eaux_irq_ctl & C2PO_IRQ_MASK)
	&&(utemp & SYS_C2PO_IRQ)) { 
	/*eaux2[6] */
	EauxIRQ_C2PO_interrupt_service();
    } 
#endif /* EAUX_ENABLE_C2PO */

#ifdef SANYOINT
    if (shadow_eaux_irq_ctl & 0x04){
	if (
#if 1
	    EAUX2_5_LOW
#else
	    (utemp & 0x10) && EAUX2_5_LOW        /*eaux2[5]*/
#endif
	    ){
	    sanyo_dsp_int();       /*sanyo direct servo*/
	} 
    }
#elif EAUX_ENABLE_16550
    if ((shadow_eaux_irq_ctl &  SP_IRQ_MASK)
	&&(utemp & SYS_SP_IRQ)) { 
	/*eaux2[6] */
	EauxIRQ_SP_interrupt_service();
    } 
#endif SANYOINT
    
}
#endif /* EAUX_IRQ */

#ifdef DSC_IRQ
static void DscIRQ_interrupt_service(void)
{
    extern int shadow_eaux_irq_ctl;
    unsigned int utemp;

    /**************************************************
       DSC_IRQ is defined
    **************************************************/
    /* New style: interrupts are connected to 3881 */
    utemp = DSC_cmd(dsc_sys_statusm, 0);

#ifdef IR 
    if (utemp & 0x04) IR_recv_interrupt_service(utemp);
#endif


#ifdef DVD_MODEM
    if ((utemp & MDMIntStatus)) {
	
	/*
	 * Clear the interrupt status bit before enabling 2nd level
	 * interrupt. Otherwise, 2nd level interrupt may bring us here again!
	 */
        int old_dsc_irq_ctl, shadow_irq_ctl2;
	extern unsigned int	shadow_irq_ctl;
	int interupt_enabled = 0;
	int savepsw, irqmask_save;
	
        old_dsc_irq_ctl = DSC_cmd(dsc_irq_ctlm, 0);
	/* disable modem interrupt */
	DSC_cmd(dsc_sys_status, MDMIntStatus);
	shadow_irq_ctl2 = old_dsc_irq_ctl & (~MDMIntMask);
#if 1
	if (!interupt_enabled) {
	    interupt_enabled = 1;
	    savepsw = get_sr();
	    irqmask_save = mvd[riface_irqmask];
	    set_sr(0x1fc3);
	    mvd[riface_irqmask] = RIFACE_LD_IRQSUPRESS | vout_irq |debug_irq;
	    DSC_cmd(dsc_irq_ctl, shadow_irq_ctl2);
	}
#endif
	if (!in_ide_dma && !talk_with_slave 
	    /*&& !in_ide_cmd_service && !ide_cmd_state*/
	    ){
	    if (modem_init_finish) DSPinterrupt();
	}
	else {
	    DebugService ++;
	    if (DebugService>=2) { 
		EPRINTF(("miss dbg %d, %d, %d, %d, %d \n",
			 DebugService,in_ide_dma,talk_with_slave,
			 in_ide_cmd_service,ide_cmd_state));
	    }
	}
#if 1
	if (interupt_enabled) {
	    mvd[riface_irqmask] = irqmask_save;
	    set_sr(savepsw);
	    DSC_cmd(dsc_irq_ctl, shadow_irq_ctl);
	    /* restore interrupt mask */
	}
#endif
    }
#endif /*DVD_MODEM */  
#ifdef DSC_ENABLE_C2PO
    if (utemp & 0x20) {
        C2PO_interrupt = 1;              /* C2PO interrupt handler      */
        DSC_cmd(dsc_sys_status, 0x20);   /* Clear 3881's interrupt      */
        mvd[riface_clear_dbgirq] = 0;    /* Clear 3210's debug_irq      */
    }
#endif
     /**************************************************
      End  DSC_IRQ 
     **************************************************/   
}
#endif /* DSC_IRQ */

 /*
 * We have many compilation flags for this service yet VCD 3.0 has a
 * separate __interrupt() routine. In order to simplify maintainance,
 * I have common routine so 3.0 can share it as well.
 */
void EXTIRQ_interrupt_service()
{
 	extern int shadow_eaux_irq_ctl;
    	unsigned int utemp;

#ifdef R4438
	utemp = mvd[eaux_sys_status] & 0xff;
#endif

#ifdef NETWORK
	if (boot_nic==0)
		WIFI_ExtIRQ_interrupt_service(utemp);
	else
		EauxIRQ_interrupt_service();
	return;
#endif
	/**************************************************
	 * Host slave communication
	**************************************************/    
#ifdef HSCOMM
	HSCOMM_recv_data();
#endif
	
#ifdef DSC_IRQ
   /**************************************************
       DSC_IRQ is defined
    **************************************************/   
	DscIRQ_interrupt_service();
	return;
#else
    /**************************************************
	 Non-DSC_IRQ 
     **************************************************/ 
#ifdef EAUX_IRQ
	EauxIRQ_interrupt_service();   
#else /* ! EAUX_IRQ */   
#ifdef IR
	IR_recv_interrupt_service(0);
#endif
#endif /* of EAUX_IRQ */  
    
#endif /* of DSC_IRQ */
	return;
}