ir.h

ESS 公司VCD软件关于IR的编程！

/* Copyright 1996, ESS Technology, Inc. */
/* SCCSID @(#)ir.h	1.5 04/09/03 */

/*
 * For mvd board, play only code
 * This is modified from version 1.17 of ir.h
 */

#ifndef _IR_H_
#define _IR_H_

#ifdef IR

#define IR_SYSCODE              0x20df
#define ASSIGN_SYSCODE          sysIRcode = IR_SYSCODE

/* State for receiving IR signals */
#ifdef IR_PHILIPS
#define IR_IDLE                 0
#define IR_LEADER               1
#define IR_CUSTOM               2
#ifdef DANCER
#define DANCER_CUSTOM           3
#endif
#endif

#if (IR_NEC || IR_SANYO)
#define IR_IDLE 		0
#define IR_LEADER_LOW 		1
#define IR_LEADER_HIGH 		2
#define IR_CUSTOM 		3
#define IR_REPEAT               4
#ifdef DANCER
#define DANCER_CUSTOM           5
#endif
#endif

#ifdef DANCER
GBLDEF0(unsigned short sysDANCERcode); /* IR's system code.             */
#endif
/* 
 * States for trasmitting IR signals. Since we do table lookup later
 * on, don't change any state assignment here.
 */
#define	IR_XMIT_IDLE		0	/* Not trasmitting anything	*/
#define	IR_XMIT_LEADER_LOW	1	/* Leader low  (9.0ms)		*/
#define	IR_XMIT_LEADER_HIGH	2	/* Leader high (4.5ms)		*/
#define	IR_XMIT_DATA		3	/* Actual data			*/
#define	IR_XMIT_GAP		4	/* Gap         (0.56ms)		*/
/* Jiang Hai loader requires a trailer (a repeat!) */
#define	IR_XMIT_REP_HIGH1	5	/* Repeat high1 (40.1ms)	*/
#define	IR_XMIT_REP_LOW1	6	/* Repeat low1  (9.1 ms)	*/
#define	IR_XMIT_REP_HIGH2	7	/* Repeat high2 (2.2 ms)	*/
#define	IR_XMIT_REP_LOW2	8	/* Repeat low2  (0.6 ms)	*/



/* The following timer values were set based on 33.9MHZ CPU clock, *
 * to fit different CPU frequencies, I use CLK_FACTOR to adjust    */
#define CLK_FACTOR      CPUCLK
/*
 * Use 8.533 us (16.67ns * 512) clock to send IR. Assume IR has 100us
 * error tolerance, I'll trigger time 40us before it should. As a result,
 * even if an interrupt sneaks in while we are sending IR code, we should
 * still be OK.
 */
#define IRW_LEADER_LOW  ((596-5)*CLK_FACTOR/339) /* 9    ms = 596 * .0151 */
#define IRW_LEADER_HIGH ((298-5)*CLK_FACTOR/339) /* 4.5  ms = 298 * .0151 */
#define IRW_GAP_LOW     ((37 -5)*CLK_FACTOR/339) /*  .56 ms =  37 * .0151 */
#define IRW_DATA_ZERO   ((37 -5)*CLK_FACTOR/339) /*  .565ms =  37 * .0151 */
#define IRW_DATA_ONE    ((112-5)*CLK_FACTOR/339) /* 1.69 ms = 112 * .0151 */


/*
 * Use 8.533 us (16.67ns * 512) clock to send IR. Assume IR has 100us 
 * error tolerance, I'll trigger time 40us before it should. As a result, 
 * even if an interrupt sneaks in while we are sending IR code, we should 
 * still be OK.
 */
#define	IRW_LEADER_LOW	((596-5)*CLK_FACTOR/339) /* 9    ms = 596 * .0151 */
#define	IRW_LEADER_HIGH	((298-5)*CLK_FACTOR/339) /* 4.5  ms = 298 * .0151 */
#define	IRW_GAP_LOW	((37 -5)*CLK_FACTOR/339) /*  .56 ms =  37 * .0151 */
#define	IRW_DATA_ZERO	((37 -5)*CLK_FACTOR/339) /*  .565ms =  37 * .0151 */
#define	IRW_DATA_ONE	((112-5)*CLK_FACTOR/339) /* 1.69 ms = 112 * .0151 */

/*
 * For JiangHai loader, there is always a "trailer" signal. If this
 * trail is missing, then the loader will not properly receive the
 * signal!
 */
#define	IRW_REP_HIGH1 ((2656)*CLK_FACTOR/339)	/* 40.1  ms =2656 * .0151 */
#define	IRW_REP_LOW1  ((603) *CLK_FACTOR/339)	/*  9.1  ms = 603 * .0151 */
#define	IRW_REP_HIGH2 ((146) *CLK_FACTOR/339)	/*  2.2  ms = 146 * .0151 */
#define	IRW_REP_LOW2  ((40)  *CLK_FACTOR/339)	/*  0.6  ms =  40 * .0151 */

#ifdef IRXMT
#ifdef	P1O
/*
 * Internal XOR gate will be used in the future
 * #define	SET_IRXOR			SET_AUX3
 * #define	CLEAR_IRXOR			CLEAR_AUX3
 * #define	IS_IRXOR_HIGH			AUX3_HIGH
 */
#define	OUTIR_LOW			CLEAR_AUX4
#define	OUTIR_HIGH			SET_AUX4
#define	TRISTATE_IR			TRISTATE_AUX4
#else
#ifdef	P2O
/*
 * Internal XOR gate will be used in the future
 * #define	SET_IRXOR			SET_AUX3
 * #define	CLEAR_IRXOR			CLEAR_AUX3
 * #define	IS_IRXOR_HIGH			AUX3_HIGH
 */
#define	OUTIR_LOW			CLEAR_AUX4
#define	OUTIR_HIGH			SET_AUX4
#define	TRISTATE_IR			TRISTATE_AUX4
#else
#ifdef	P3O
/*
 * Internal XOR gate will be used in the future
 * #define	SET_IRXOR			SET_AUX5
 * #define	CLEAR_IRXOR			CLEAR_AUX5
 * #define	IS_IRXOR_HIGH			AUX5_HIGH
 */
#define	OUTIR_LOW			CLEAR_AUX2
#define	OUTIR_HIGH			SET_AUX2
#define	TRISTATE_IR			TRISTATE_AUX2
#else
#ifdef	P4O
#define	OUTIR_LOW			CLEAR_AUX7
#define	OUTIR_HIGH			SET_AUX7
#define	TRISTATE_IR			TRISTATE_AUX7
#endif	/* P4O */
#endif	/* P3O  */
#endif	/* P2O */
#endif	/* P1O */
#endif	/* IRXMT */

EXPORT	char			tblKillIR[];
EXPORT	unsigned int		resend_delay;


#ifdef IRXMT
GBLDEF(char connect_inout, 0);	/* IR input and output are two		*
				 * different signals (i.e. 3208 is	*
				 * responsible for output the IR signal)*/
#endif
GBLDEF(unsigned short sysIRcode, 0); /* IR's system code.		*/

/************************************************************
 * global functions to be exported
 ************************************************************/
EXPORT	void			IR_init();
EXPORT	void			IR_send_FB();
EXPORT	void			IR_send_FF();
EXPORT	void			IR_send_Next();
EXPORT	void			IR_send_Pause();
EXPORT	void			IR_send_Play();
EXPORT	void			IR_send_data(unsigned char, int);
EXPORT	void			processKeycode();
EXPORT	void			IR_xmit_interrupt_service(void);
EXPORT  void                    IR_recv_interrupt_service(unsigned int);

#endif	/* IR */
/* in master and slave, we need codeIR */
GBLDEF(unsigned short codeIR, 0); /* Final IR code (OR with 0x100)	*/
#endif	/* _IR_H_	*/