cstartxf.asm

ccp

	SYSC_M_H	EQU	07BH	; Mask high byte SYSCON.
@ENDI
	
	; Predefined functions for register R1, R2 and R3.
	POF_RAM		LIT	'R1'	; Page offset address ram data.
	SOF_RAM		LIT	'R1'	; Segment offset address ram data.
	SOF_RAM_H	LIT	'RH1'	; Segment address high byte.
	POF_ROM		LIT	'R2'	; Page offset address rom data.
	SOF_ROM		LIT	'R2'	; Segment offset address rom data.
	SOF_ROM_H	LIT	'RH2'	; Segment address high byte.
	BP_RAM		LIT	'R3'	; Bit position ram data

;*****************************************************************************
;* __CSTART
;*****************************************************************************
__CSTART_PR	SECTION CODE WORD PUBLIC 'CPROGRAM'
__CSTART 	PROC TASK __CSTART_TASK INTNO __CSTART_INUM = 00H

	DISWDT				; Disable watchdog timer.


						; Set SYSCON register.
	;BFLDL	SYSCON, #SYSC_M_L, #(SYSC_L AND SYSC_M_L)
	;BFLDH	SYSCON, #SYSC_M_H, #(SYSC_H AND SYSC_M_H)
        MOV     SYSCON, #0004h          ; 256 Word Stack, XRAM enabled

        ;MOV     SYSCON, #0000h          ; 256 Word Stack, XRAM disabled
@IF( @C167 )
						; Set BUSCON0 register.
	;BFLDL	BUSCON0, #BUSC0_M_L, #(BUSC0_L AND BUSC0_M_L)
	;BFLDH	BUSCON0, #BUSC0_M_H, #(BUSC0_H AND BUSC0_M_H)
@ENDI
        MOV     BUSCON0, #049Dh         ; FlashEPROM, 2 Waitstates

        MOV     ADDRSEL1, #0406h        ; RAM 256 kByte with Flash
        MOV     BUSCON1, #049Dh	        ; first addrsel, then buscon


        ;MOV     ADDRSEL2, #0000h        ;
        ;MOV     BUSCON2,  #0000h        ; unused, to avoid memory malfunction
        ;MOV     ADDRSEL3, #0000h        ;
        ;MOV     BUSCON3,  #0000h        ;

        MOV     ADDRSEL4, #0806h        ; Start 0x80000: size 255
        MOV     BUSCON4, #0440h	        ; extern Bus enable ;8 bit multiplexed;
                                        ; 15 Waitstates

	MOV	STKOV,	#?SYSSTACK_BOTTOM + 6*2	; Set stack underflow pointer.
	MOV	STKUN,	#?SYSSTACK_TOP		; Set stack overflow pointer.
	MOV	SP,	#?SYSSTACK_TOP		; Set stack pointer.

	MOV	CP, 	#osek_sys_rb		; Set context pointer.  ####2####
@IF( NOT @C167 )
	BSET	P3.13			; Set WR output high.
	BSET	DP3.13			; enable output of WR strobe.
@ENDI
	EINIT				; End of initialization
      
        MOV     DP8, #0FFh  ;     /* digital outputs   */
        MOV     P8,  #0FFh  ;     /* alle dig outs aus */

        ;MOV     DPP0, #PAG _bRestartFromError
        ;MOV     R0,   #POF _bRestartFromError
        ;MOV     R1,   #0
        ;MOVB    [R0], RL1
RECOVERY: LABEL FAR
	MOV	STKOV,	#?SYSSTACK_BOTTOM + 6*2	; Set stack underflow pointer.
	MOV	STKUN,	#?SYSSTACK_TOP		; Set stack overflow pointer.
	MOV	SP,	#?SYSSTACK_TOP		; Set stack pointer.

	MOV	CP, 	#osek_sys_rb		; Set context pointer.  ####2####

@IF( @EVA )
	BOTTOM_BITRAM	LIT  '0FD4CH'	; 0FD00H - 0FD4BH is monitor data area
@ELSE
	BOTTOM_BITRAM	LIT  '0FD00H'
@ENDI
					; Clear bit addressable memory
	MOV	R0, #0FDFEH		; R0 = top of bit addressable area
loop:	CMP	R0, #osek_sys_rb        ; if( R0 in bit addressable area )      ####2####
	JMP	CC_EQ, cbclr		; then continue next (bit) word clear.
	MOV	[R0], zeros		; clear
cbclr:	CMPD2	R0, # BOTTOM_BITRAM	; if( not bottom bit addressable area )
	JMP	CC_NE, loop		; then continue next (bit) word clear

	; The following code is needed for initialization of static variables
@IF( @EQS(@MODEL,"SMALL") )
	MOV	DPP0, #PAG ?BASE_DPP0	; Set data page pointer.
	MOV	DPP1, #PAG ?BASE_DPP1	;
	MOV	DPP2, #PAG ?BASE_DPP2	;
@ENDI
					 ; C166_INIT
@IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") | @EQS(@MODEL,"SMALL") )
	MOV	R4,  #POF ?C166_INIT_HEAD ; move intra-page offset address rom
					 ; data section C166_INIT to R4
INIT_DPP0:				 ;
	MOV	DPP0,#PAG ?C166_INIT_HEAD ; load data page pointer register DPP0
					 ; with data page of rom data C166_INIT
	NOP				 ; delay for pipeline effect
@ENDI
@IF( @EQS( @MODEL, "TINY" ) )
	MOV	R4, #?C166_INIT_HEAD	; move intra-segment offset address of
					; rom data section C166_INIT to R4
@ENDI
INIT:					;
	MOV	R5, [R4+]		; INIT block header code -> R5
	CMP	R5, #01H		; check if header code 1 (bit)
	JMP	CC_EQ, INIT_01		;

@IF( @EQS(@MODEL,"TINY") | @EQS(@MODEL,"SMALL") )
	CMP	R5, #05H		; check if header code is 5 (near)
    @IF( @EQS(@MODEL,"SMALL") )
	JMP	CC_EQ, INIT_05		;
    @ELSE
	JMP	CC_NE, INIT_END		; if(no header code) end initialization
    @ENDI
@ENDI
@IF( @EQS(@MODEL,"MEDIUM") | @EQS(@MODEL,"LARGE") | @EQS(@MODEL,"SMALL") )
	CMP	R5, #06H		; check if header code 6 (far)
	JMP	CC_EQ, INIT_06		;
	CMP	R5, #07H		; check if header code 7 (huge)
	JMP	CC_NE, INIT_END		; if(no header code) end initialization

INIT_07:				; initialize huge ram data. (data > 64K)
	MOV	SOF_RAM, [R4+]		; move intra-segment offset address ram
					; data block to SOF_RAM=R1
	MOV	R3, [R4+]		; move segment address ram data block 
					; to register R3
					; process data page number ram data
	MOV	RH3, SOF_RAM_H		; R3.15:14=lower order bits of data page
	ROL	R3, #2			; R3.3:2:1:0 = data page number
	AND	R3, #0FH		; clr bit R3.15 to bit R3.4
	MOV	DPP1, R3		; load data page pointer register DPP1
					; with data page of ram data block
	BFLDH	SOF_RAM, #0C0H, #040H	; DPP1:POF_RAM ->SOF_RAM=R1
					;
	MOV	SOF_ROM, [R4+]		; move intra-segment offset address rom
					; data block to SOF_ROM=R2
	MOV	R3, [R4+]		; move segment address rom data block
					; to R3
					; process data page number rom data
	MOV	RH3, SOF_ROM_H		; R3.15:14=lower order bits of data page
	ROL	R3, #2			; R3.3:2:1:0 = data page number
	AND	R3, #0FH		; clr bit R3.15 to bit R3.4
	MOV	DPP2, R3		; load data page pointer register DPP2
					; with data page of rom data block
	BFLDH	SOF_ROM, #0C0H, #080H	; DPP2:POF_ROM ->SOF_ROM=R2
					;
	MOV	R5, [R4+]		; number of bytes (R6:R5) to move from
	MOV	R6, [R4+]		; rom to ram. MSW=R6, LSW=R5 (long word)
					;
MB07_3:	CMPD1	R5, #0			; test if all bytes are moved and
	JMP	CC_NE, MB07_1 		; decrement number of bytes to move.
	CMPD1	R6, #0			;
@IF( @EQS( @MODEL, "SMALL" ) )
	JMP	CC_EQ, MB07_4		;
@ELSE
	JMP	CC_EQ, INIT		; if( block end ) next initialization
@ENDI
MB07_1:	MOVB	[SOF_RAM], [SOF_ROM]	; move byte from rom to ram
	CMPI1	SOF_RAM, #07FFFH	; test end of data page and inc SOF_RAM
	JMP	CC_NE, MB07_2		; if(no page end) cont init current page
	MOV	SOF_RAM, #04000H	; preset offset address ram data
	ADD	DPP1, #1		; next page of ram data; increment DPP1
MB07_2:	CMPI1	SOF_ROM, #0BFFFH	; test end of page and inc SOF_ROM
	JMP	CC_NE, MB07_3		; if(no page end) cont init current page
	MOV	SOF_ROM, #08000H	; preset offset address rom data
	ADD	DPP2, #1		; next page of rom data; increment DPP2
	JMP	CC_UC, MB07_3		; jump for next byte move
@IF( @EQS( @MODEL, "SMALL" ) )
MB07_4:	MOV 	DPP1, #PAG ?BASE_DPP1	; restore data page register DPP1 and
	MOV 	DPP2, #PAG ?BASE_DPP2	; DPP2 to their default values.
	JMP	CC_UC, INIT		; next initialization
@ENDI

INIT_06:				; initialize far ram data. (CPU mode 
					; is segmented with DPP usage linear
					; or paged.)
	MOV	POF_RAM, [R4+]		; move intra-page offset address ram
					; data block to POF_RAM=R1
	BFLDH	SOF_RAM, #0C0H, #040H	; DPP1:POF_RAM ->SOF_RAM=R1
	MOV	DPP1, [R4]		; load data page pointer register DPP1
					; with data page of ram data block
	ADD	R4, #2			; inc offset address to ram data section
					; C166_INIT and also insure a delay for
					; pipeline effect.(DPP1 set)
					;
	MOV	POF_ROM, [R4+]		; move intra-page offset address rom
					; data block to POF_ROM=R2
	BFLDH	SOF_ROM, #0C0H, #080H	; DPP2:POF_ROM ->SOF_ROM=R2
	MOV	DPP2, [R4]		; load data page pointer register DPP2
					; with data page of rom data block
	ADD	R4, #2			; inc offset address to rom data section
					; C166_INIT and also insure a delay for
					; pipeline effect.(DPP2 set)
					;
	MOV	R5, [R4+]		; number of bytes to move from rom to
					; ram for specified data block.
					;
MB06_1:	CMPD1	R5, #0			; test on data block end
@IF( @EQS( @MODEL, "SMALL" ) )
	JMP	CC_EQ, MB06_2		;
@ELSE
	JMP	CC_EQ, INIT		; if( block end ) next initialization
@ENDI
	MOVB	[SOF_RAM], [SOF_ROM+]	; move byte from rom to ram, inc SOF_ROM
	ADD	SOF_RAM, #1		; inc SOF_RAM
	JMP	CC_UC, MB06_1		; jump for next byte move
@IF( @EQS( @MODEL, "SMALL" ) )
MB06_2:	MOV 	DPP1, #PAG ?BASE_DPP1	; restore data page register DPP1 and
	MOV 	DPP2, #PAG ?BASE_DPP2	; DPP2 to their default values.
	JMP	CC_UC, INIT		; next initialization
@ENDI
@ENDI

@IF( @EQS(@MODEL,"TINY") | @EQS(@MODEL,"SMALL") )
INIT_05:				; initialize near ram data. (DPP usage
					; is linear, CPU mode is segmented
					; for SMALL memory model and not
					; segmented for TINY memory model.)
	MOV	SOF_RAM, [R4+]		; move intra-segment offset address ram
					; data block to SOF_RAM=R1
					;
	MOV	SOF_ROM, [R4+]		; move intra-segment offset address rom
					; data block to SOF_ROM=R2
					;
	MOV	R5, [R4+]		; number of bytes to move from rom to
					; ram for specified data block.
@IF( @EQS( @MODEL, "SMALL" ) )
	MOV	DPP0, #PAG ?BASE_DPP0	; restore DPP0 to its default value
@ENDI
MB05_1:	CMPD1	R5, #0			; test on data block end, and delay
					; for pipeline effect if DPP0 is
					; restored for SMALL memory model.
@IF( @EQS( @MODEL, "TINY" ) )
	JMP	CC_EQ, INIT 		; if( block end ) next initialization
@ELSE
	JMP	CC_EQ, INIT_DPP0	; if( block end ) reload data page
					; pointer register DPP0 with data page
					; of rom data C166_INIT and start next
					; initialization.
@ENDI
	MOVB	[SOF_RAM], [SOF_ROM+]	; byte move rom to ram, inc SOF_ROM
	ADD	SOF_RAM, #1		; inc SOF_RAM
	JMP	CC_UC, MB05_1		; jump for next byte move
@ENDI

@IF( @BIT_INIT )
INIT_01:				; initialize bit data.
	MOV	BP_RAM, [R4+]		; move bit position ram data block to 
					; BOF_RAM=R3
	MOV	POF_RAM, [R4+]		; mov bit offset address ram data block
					; to POF_RAM=R1
@IF( @EQS( @MODEL, "TINY" ) )
	MOV	R5, [R4+]		; move data page of ram data block to R5
	SHL	R5, #14			; position page number
	OR	SOF_RAM, R5		; intra-segment offset address to 
					; SOF_RAM = R1
@ELSE
	BFLDH	SOF_RAM, #0C0H, #040H	; DPP1:POF_RAM ->SOF_RAM=R1
	MOV	DPP1, [R4]		; load data page pointer register DPP1
					; with data page of ram data block
	ADD	R4, #2			; inc offset address to ram data section
					; C166_INIT and also insure a delay for
					; pipeline effect.(DPP1 set)
@ENDI
					;
	MOV	POF_ROM, [R4+]		; move intra-page offset address rom
					; data block to POF_ROM=R2
@IF( @EQS( @MODEL, "TINY" ) )
	MOV	R5, [R4+]		; move data page of rom data block to R5
	SHL	R5, #14			; position page number
	OR	SOF_ROM, R5		; intra-segment offset address to 
					; SOF_ROM=R2
@ELSE
	BFLDH	SOF_ROM, #0C0H, #080H	; DPP2:POF_ROM ->SOF_ROM=R2
	MOV	DPP2, [R4]		; load data page pointer register DPP2
					; with data page of rom data block
	ADD	R4, #2			; inc offset address to rom data section
					; C166_INIT and also insure a delay for
					; pipeline effect.(DPP2 set)
@ENDI
					;
	MOV	R5, [R4+]		; number of bits to initialize.
					; start init bit block
NBBI:					; next bit block init
	CMP	BP_RAM, #0		; if ( bitpointer != 0 )
	JMP	cc_NZ, BPNZ		;   then bit pointer not at 0 location
	CMP	R5, #16			; if ( initbits < 16 )
	JMP	cc_ULT, LT16		;   then init bitblock < 16 bits
					;   else init bitblock = 16 bits
	MOV	R9, #16			; bitblocksize = 16
	SUB	R5, R9			; initbits -= bitblocksize
	JMP	cc_UC, STBINIT		; start bit initialization
LT16:					; bit block to init < 16 bits
	MOV	R9, R5			; bitblocksize = initbits
					; initbits = 0
	MOV	R5, #0			; bits left to initialize is zero