init.s

4510下的串口扩展

;************************************************************************************************
;WorkGroup:		Institute of Automation,Chinese Academy of Sciences
;File Name:		Init.s
;Description:		Timer interrupt test. 
;Author:			Lee JuGuang
;Date&Time:		2003-10-18	19:56
;SDRAM Configuration:	Use ljg.txt,SDRAM remap to address 0x0~0x100,0000(16MB) 
;************************************************************************************************	
	GET	mem.a
	GET	casia1.a
	IMPORT Main
	CODE32
	AREA    Init,CODE,READONLY
	ENTRY 
	

	B       Reset_Handler		
        	B       .;
        	B       .;
        	B       .;
        	B       .;
	NOP      
        	B       .;
        	B       .;


Reset_Handler

	LDR	r0, =ASIC_BASE		 
	LDR	r1, =0xE7FFFFA0	;Start_addr = 0x3FE00000
	STR	r1, [r0]	  	;8K SRAM

;******************************************************	
;Mask all interrupt
;******************************************************
	LDR 	R2,=0x3fffff
	LDR	R3,=0x3ff4008
	STR	R2,[R3]

;*******************************************************
;Disable all interrupt
;*******************************************************
	MRS	R0,CPSR
	BIC	R0,R0,#MODE_MASK
	ORR	R0,R0,#SUP_MODE
	ORR	R0,R0,#IBit
	ORR	R0,R0,#FBit 
	MSR	CPSR_cf,R0
	
;******************************************************
;Initialise system stack for different processor modes
;******************************************************
	MRS	r0, cpsr
	BIC	r0, r0, #LOCKOUT | MODE_MASK
	ORR	r2, r0, #USR_MODE	
	ORR	r1, r0, #LOCKOUT | FIQ_MODE

	MSR	cpsr_c, r1				;/* change to FIQ MODE */
	MSR	spsr_c, r2 				;/* set the SPSR under FIQ */
	LDR	sp, =FIQ_STACK				;/* set SP (R13) under FIQ */

	ORR	r1, r0, #LOCKOUT | IRQ_MODE
	MSR	cpsr_c, r1				;/* change to IRQ MODE */
	MSR	spsr_c, r2				;/* set the SPSR under IRQ */
	LDR	sp, =IRQ_STACK				;/* set SP (R13) under IRQ */

	ORR	r1, r0, #LOCKOUT | ABT_MODE
	MSR	cpsr_c, r1				;/* change to ABORT MODE */
	MSR	spsr_c, r2				;/* set the SPSR under ABORT */
	LDR	sp, =ABT_STACK				;/* set SP (R13) under ABORT */

	ORR	r1, r0, #LOCKOUT | UDF_MODE
	MSR	cpsr_c, r1				;/* change to Undefine MODE */
	MSR	spsr_c, r2				;/* set the SPSR under Undefine */
	LDR	sp, =UDF_STACK				;/* set SP (R13) under Undefine */

	ORR	r1, r0, #LOCKOUT | SUP_MODE
	MSR	cpsr_c, r1				;/* change to Superuser MODE */
	MSR	spsr_c, r2				;/* set the SPSR under super */ 
	LDR	sp, =SUP_STACK		

	MRS	r0, cpsr
	BIC	r0, r0, #LOCKOUT | MODE_MASK
	ORR	r1, r0, #USR_MODE	
	MSR	CPSR_cf,R0
	LDR	SP,=USR_STACK
;********************************************************
;FLASH SDRAM RAM setting
;********************************************************
	LDR      r1, =0x00103006 
	LDR      r2, =0x12040060 		;pu tong ROM 1000000-1200000	ROMCON0	
	mov	r3, #0x60
	mov      r4, #0x60
	mov      r5, #0x60
	mov      r6, #0x60
	mov      r7, #0x60
	LDR      r8, =0x10000380 		;0000000-1000000			DRAMCON0
	mov      r9, #0
	mov      r10, #0
	mov      r11, #0
	LDR      r12, =0xce338220
	LDR      r0,  =0x03ff3010 	 			
	STMIA	r0, {r1-r12}
;********************************************************
;Timer setting
;********************************************************
	LDR	R1,=0x3FF6000
	LDR	R0,=&01
	STR	R0,[R1]				;use timer0

	LDR	R1,=0x3FF6004
	LDR	R0,=&3FFFFF
	STR	R0,[R1]				;the timer0 reg current 

;********************************************************
;Mask off all IRQ sources
;********************************************************


	LDR	R1,=INTMOD
	LDR	R0,=&0
	STR	R0,[R1]
	
**********************************************************
	BL	Main
	B	.
*********************************************************
	
	END