snds.s

一个ARM7的定时器程序,程序员通过该程序可以了解ARM7的编程方法,启动过程,地址映射等基本概念和实现方法

;/*************************************************************************/
;/* Format of the Program Status Register                                 */
;/*************************************************************************/
;/*                                                                       */
;/* 31  30  29   28         7   6   5   4   3   2   1   0                 */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
;/*| N | Z | C | V |      | I | F | T |     M4 ~ M0       |               */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
;/*                                                                       */
;/* Processor Mode and Mask                                               */
;/*                                                                       */
;/*************************************************************************/
;

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F 
MASK_MODE		EQU		0x000000FF
MODE_SVC32		EQU		0x00000013
I_BIT           EQU     0x80 ; when I bit is set, IRQ is disabled
F_BIT           EQU     0x40 ; when F bit is set, FIQ is disabled
LOCKOUT			EQU		0xC0
ASIC_BASE  	 	EQU 	0x03ff0000

;SYSTEM MANAGER REGISTERS 
ARM7_SYSCFG	    EQU 	(ASIC_BASE+0x0000)
ARM7_CLKCON  	EQU 	(ASIC_BASE+0x3000)
ARM7_EXTACON0   EQU 	(ASIC_BASE+0x3008)
ARM7_EXTACON1   EQU 	(ASIC_BASE+0x300c)
ARM7_EXTDBWTH   EQU 	(ASIC_BASE+0x3010)
ARM7_ROMCON0  	EQU 	(ASIC_BASE+0x3014)
ARM7_ROMCON1  	EQU 	(ASIC_BASE+0x3018)
ARM7_ROMCON2  	EQU 	(ASIC_BASE+0x301c)
ARM7_ROMCON3  	EQU 	(ASIC_BASE+0x3020)
ARM7_ROMCON4  	EQU 	(ASIC_BASE+0x3024)
ARM7_ROMCON5  	EQU 	(ASIC_BASE+0x3028)
ARM7_DRAMCON0   EQU 	(ASIC_BASE+0x302c)
ARM7_DRAMCON1   EQU 	(ASIC_BASE+0x3030)
ARM7_DRAMCON2   EQU 	(ASIC_BASE+0x3034)
ARM7_DRAMCON3   EQU 	(ASIC_BASE+0x3038)
ARM7_REFEXTCON  EQU 	(ASIC_BASE+0x303c)

; controller registers
ARM7_INTMODE 	EQU 	(ASIC_BASE+0x4000)
ARM7_INTPEND 	EQU 	(ASIC_BASE+0x4004)
ARM7_INTMASK 	EQU 	(ASIC_BASE+0x4008)
ARM7_INTOFFSET  EQU 	(ASIC_BASE+0x4024)
ARM7_INTPENDTST EQU  	(ASIC_BASE+0x402c)

ARM7_INTPRI0 	EQU 	(ASIC_BASE+0x400C)
ARM7_INTPRI1 	EQU 	(ASIC_BASE+0x4010)
ARM7_INTPRI2 	EQU 	(ASIC_BASE+0x4014)
ARM7_INTPRI3 	EQU 	(ASIC_BASE+0x4018)
ARM7_INTPRI4 	EQU 	(ASIC_BASE+0x401C)
ARM7_INTPRI5 	EQU 	(ASIC_BASE+0x4020)

ARM7_INTOSET_FIQ  	EQU 	(ASIC_BASE+0x4030)
ARM7_INTOSET_IRQ  	EQU 	(ASIC_BASE+0x4034)


; I/O Port Interface  
ARM7_IOPMOD 		EQU 	(ASIC_BASE+0x5000)
ARM7_IOPCON 	 	EQU 	(ASIC_BASE+0x5004)
ARM7_IOPDATA 		EQU 	(ASIC_BASE+0x5008)

; IIC Registers 
ARM7_IICCON    		EQU  	(ASIC_BASE+0xf000)
ARM7_IICBUF    		EQU  	(ASIC_BASE+0xf004)
ARM7_IICPS     		EQU 	(ASIC_BASE+0xf008)
ARM7_IICCNT    		EQU 	(ASIC_BASE+0xf00c)

; UART0 Registers
ARM7_ULCON0			EQU	(ASIC_BASE+0xD000)
ARM7_UCON0			EQU	(ASIC_BASE+0xD004)
ARM7_USTAT0			EQU	(ASIC_BASE+0xD008)
ARM7_UTXBUF0		EQU	(ASIC_BASE+0xD00C)
ARM7_URXBUF0		EQU	(ASIC_BASE+0xD010)
ARM7_UBRDIV0		EQU (ASIC_BASE+0xD014)


; Timer Register  

ARM7_TMOD			EQU	(ASIC_BASE+0x6000)
ARM7_TDATA0			EQU	(ASIC_BASE+0x6004)
ARM7_TDATA1			EQU	(ASIC_BASE+0x6008)
ARM7_TCNT0			EQU	(ASIC_BASE+0x600c)
ARM7_TCNT1			EQU	(ASIC_BASE+0x6010)


;/*************************************************************************/
;/*  SYSTEM MEMORY CONTROL REGISTER EQU TABLES                            */
;/*************************************************************************/

;***************Memory Init************
rSYSCFG			EQU		0xE7ffffA0
rEXTDBWTH		EQU		0x00002002
rROMCON0		EQU		0x02000060
rROMCON1  		EQU  	0x60
rROMCON2   		EQU  	0x60
rROMCON3   		EQU  	0x60
rROMCON4   		EQU  	0x60
rROMCON5   		EQU  	0x60
rSDRAMCON0   	EQU  	0x18040390
rSDRAMCON1   	EQU  	0x00
rSDRAMCON2   	EQU  	0x00
rSDRAMCON3   	EQU  	0x00
rSREFEXTCON		EQU		0xCE278360

	
;************Memory Remap**************
rEXTDBWTH_R		EQU		0x00002002
rROMCON0_R		EQU		0x12040060
rROMCON1_R  	EQU  	0x60
rROMCON2_R   	EQU  	0x60
rROMCON3_R   	EQU  	0x60
rROMCON4_R   	EQU  	0x60
rROMCON5_R   	EQU  	0x60
rSDRAMCON0_R   	EQU  	0x08000390
rSDRAMCON1_R   	EQU  	0x00
rSDRAMCON2_R   	EQU  	0x00
rSDRAMCON3_R   	EQU  	0x00
rSREFEXTCON_R	EQU		0xCE278360

;/***************************************************************/
;/*************************************************************************/
;/*  SYSTEM STACK MEMORY  : 8K bytes system stacks are defined at memory.a
;/*************************************************************************/

STACK_BASE		EQU		0x03fe2000

USR_STACK_SIZE  EQU     1024 
UDF_STACK_SIZE  EQU      512 
ABT_STACK_SIZE  EQU      512 
IRQ_STACK_SIZE  EQU     2048 
FIQ_STACK_SIZE  EQU     2048 
SVC_STACK_SIZE  EQU     2048      

FIQ_STACK		EQU		STACK_BASE 					;0x03FE2000
IRQ_STACK		EQU		FIQ_STACK - FIQ_STACK_SIZE	;0x03FE1800
ABT_STACK		EQU		IRQ_STACK - IRQ_STACK_SIZE	;0x03FE1000
UDF_STACK		EQU		ABT_STACK - ABT_STACK_SIZE	;0x03FE0E00
USR_STACK		EQU		UDF_STACK - UDF_STACK_SIZE	;0x03FE0C00
SVC_STACK		EQU		USR_STACK - USR_STACK_SIZE	;
     
       END