pcmdrv.h

pcmic初始代码！

#ifndef _PCMCIA_DRV_H
#define _PCMCIA_DRV_H

/* GLASIEA inf. */
typedef struct {
    volatile unsigned short ODR;        /* Output */
    volatile unsigned short MFODR;      /* Muliti function Output */
    volatile unsigned short DIR;        /* Direction */
    volatile unsigned short MFDIR;      /* Muliti function Output */
    volatile unsigned short dumy1;
    volatile unsigned short MFSEL;      /* Muliti function Select */
    volatile unsigned short IDR;        /* Input */
    volatile unsigned short MFIDR;      /* Muliti function Output */
    volatile unsigned short PIER;       /* Positive interrupt Enable */
    volatile unsigned short MFPIER;     /* MF Positive interrupt Enable */
    volatile unsigned short NIER;       /* Negative interrupt Enable */
    volatile unsigned short MFNIER;     /* MF Negative interrupt Enable */
    volatile unsigned short PISR;       /* Positive interrupt Status/Clear */
    volatile unsigned short MFPISR;     /* MF Positive interrupt Status/Clear */
    volatile unsigned short NISR;       /* Negative interrupt Status/Clear */
    volatile unsigned short MFNSR;      /* MF Negative interrupt Status/Clear */
    volatile unsigned short CTRL;       /* control */
} GLASIEA_REG;

/* I/O Data Out Register,                       Offset 0x00 */
#define GR_IO_DOUT_MASK          0xFF1F
/* MFIO Data Out Register,                      Offset 0x02 */
#define GR_MIO_DOUT_MASK         0xFF07
/* I/O Direction Register,                      Offset 0x04 */
#define GR_IO_DIRECT_MASK        0xFF1F
/* MFIO Direction Register,                     Offset 0x06 */
#define GR_MIO_DIRECT_MASK       0xFF07
/*  Reseved,                                    Offset 0x08 */

/* MFIO Select Register,                        Offset 0x0A */
#define GR_MIO_SELECT_MASK       0xFF07
/* I/O Data Input Register,                     Offset 0x0C */
#define GR_IO_DIN_MASK           0xFF1F
/* MFIO Data Input Register,                    Offset 0x0E */
#define GR_MIO_DIN_MASK          0xFF07
/* I/O Positive Input Enable Register,          Offset 0x10 */
#define GR_IO_POS_ENBL_MASK      0xFF1F
/* MFIO Positive Input Enable Register,         Offset 0x12 */
#define GR_MIO_POS_ENBL_MASK     0xFF07
/* I/O NEGATIVE Input Enable Register,          Offset 0x14 */
#define GR_IO_NEG_ENBL_MASK      0xFF1F
/* MFIO Positive Input Enable Register,         Offset 0x16 */
#define GR_MIO_NEG_ENBL_MASK     0xFF07
/* I/O Positive Interrupt Status Register,      Offset 0x18 */
#define GR_IO_POS_STATUS_MASK    0xFF1F
/* I/O Positive Interrupt Clear Register,       Offset 0x18 */
#define GR_IO_POS_CLEAR_MASK     0xFF1F
/* MFIO Positive Interrupt Status Register,     Offset 0x1A */
#define GR_MIO_POS_STATUS_MASK   0xFF07
/* MFIO Positive Interrupt Clear Register,      Offset 0x1A */
#define GR_MIO_POS_CLEAR_MASK    0xFF07
/* IO Negative Interrupt Status Register,       Offset 0x1C */
#define GR_IO_NEG_STATUS_MASK    0xFF1F
/* IO Negative Interrupt Clear Register,        Offset 0x1C */
#define GR_IO_NEG_CLEAR_MASK     0xFF1F
/* MFIO Negative Interrupt Status Register,     Offset 0x1E */
#define GR_MIO_NEG_STATUS_MASK   0xFF07
/* IO Negative Interrupt Clear Register,        Offset 0x1E */
#define GR_MIO_NEG_CLEAR_MASK    0xFF07
/* Control Register,                            Offset 0x20 */

// MFIO Negtive interrupt Status/Clear Register
// 蔼