makefile

SystemC to Verilog 转换源程序。

#  This program is free software; you can redistribute it and/or modify
#  it under the terms of the GNU General Public License as published by
#  the Free Software Foundation; either version 2 of the License, or
#  (at your option) any later version.
#
#  This program is distributed in the hope that it will be useful,
#  but WITHOUT ANY WARRANTY; without even the implied warranty of
#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#  GNU Library General Public License for more details.
#
#  You should have received a copy of the GNU General Public License
#  along with this program; if not, write to the Free Software
#  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA02111-1307, USA.

LEX = flex
all:
	cd src; make all

test: 
	cd src; make all
	cd examples; ../bin/sc2v.sh rng; ../bin/sc2v.sh md5; echo ""; echo "sc2v translated the following files successfully"; echo ""; ls -l *.v 

docs:
	cd src; doxygen doxygen.cfg 

clean:
	\rm -r docs; cd src; make clean