encrypt_and_hash_example.dwp

网络处理器例子程序3

# Developer Workbench Project File
# Format Version 31.91
#********  Do not edit this file ***********

# Begin Project encrypt_and_hash_example
CHIP_TYPE = 10
DEBUG_ONLY = FALSE
PROJECT_PATH = C:\ixa_3.0\src\EXAMPLES\microcode\encrypt_and_hash_example\
MIN_REVISION_NUM = 0
MAX_REVISION_NUM = -1
ASSEMBLER_INCLUDE = ..\..\..\library\dataplane_library\microcode\

# Begin Group Source Files

# Begin Source File
PATH = ..\..\..\library\dataplane_library\microcode\constants.uc
# End Source File

# Begin Source File
PATH = ..\..\..\library\dataplane_library\microcode\crypto.h
# End Source File

# Begin Source File
PATH = ..\..\..\library\dataplane_library\microcode\crypto.uc
# End Source File

# Begin Source File
PATH = ..\..\..\library\dataplane_library\microcode\crypto_messages.h
# End Source File

# Begin Source File
PATH = .\encrypt_and_hash_example.uc
# End Source File

# Begin Source File
PATH = ..\..\..\library\dataplane_library\microcode\stdmac.uc
# End Source File
# End Group Source Files

# Begin Group Script Files
# End Group Script Files

# Begin Debug Startup Options
DO_MODEL_INIT = TRUE
SIM_STEP_UNIT = Core
# End Debug Startup Options

# Begin Chip 

# Begin Chip Configuration Info

# Begin Clock Frequencies
USE_STANDARD_FREQ = TRUE
STANDARD_FREQ_INDEX = 2
CUSTOM_CLK_FREQ = 2800
SRAM0_DIVISOR = 0
SRAM1_DIVISOR = 0
SRAM2_DIVISOR = 0
SRAM3_DIVISOR = 0
DRAM_DIVISOR = 0
MSF_DIVISOR = 0
APB_DIVISOR = 0
PCI_BUS_CLK_FREQ = 66
MSF_EXT1_CLK_FREQ = 0
MSF_EXT2_CLK_FREQ = 0
MSF_EXT3_CLK_FREQ = 0
USE_MSF_EXT_CLOCK = FALSE
# End Clock Frequencies

# Begin Memory Configuration Info
DRAM_CHANNEL_COUNT = 3
DRAM_CHANNEL_SIZE = 64
SRAM_CHANNEL0_PART_COUNT = 1
SRAM_CHANNEL0_PART_SIZE = 64
SRAM_CHANNEL1_PART_COUNT = 1
SRAM_CHANNEL1_PART_SIZE = 64
SRAM_CHANNEL2_PART_COUNT = 1
SRAM_CHANNEL2_PART_SIZE = 64
SRAM_CHANNEL3_PART_COUNT = 1
SRAM_CHANNEL3_PART_SIZE = 64
# End Memory Configuration Info
# End Chip Configuration Info

# Begin MicroEngine 0
# End MicroEngine

# Begin MicroEngine 1
# End MicroEngine

# Begin MicroEngine 2
# End MicroEngine

# Begin MicroEngine 3
# End MicroEngine

# Begin MicroEngine 4
# End MicroEngine

# Begin MicroEngine 5
# End MicroEngine

# Begin MicroEngine 6
# End MicroEngine

# Begin MicroEngine 7
# End MicroEngine

# Begin MicroEngine 8
# End MicroEngine

# Begin MicroEngine 9
# End MicroEngine

# Begin MicroEngine 10
# End MicroEngine

# Begin MicroEngine 11
# End MicroEngine

# Begin MicroEngine 12
# End MicroEngine

# Begin MicroEngine 13
# End MicroEngine

# Begin MicroEngine 14
# End MicroEngine

# Begin MicroEngine 15
# End MicroEngine
# End Chip

# Begin Assembler Settings
ASSEMBLY_REQUIRED = FALSE
ROOT_FILE = .\encrypt_and_hash_example.uc
OPTIMIZE = 0
WARNING_LEVEL = 3
CONVERT_WARNINGS = FALSE
REQUIRE_REG_DECLARATIONS = TRUE
CASE_SENSITIVE = TRUE
DEBUG_INFO = TRUE
AUTO_FIX_BANK_CONFLICTS = FALSE
OUTPUT = .\encrypt_and_hash_example.list
LOCAL_MEMORY_START = 0
ADDITIONAL_OPTIONS = 
# End Assembler Settings

# Begin Linker Settings
LINK_REQUIRED = FALSE
CHIP_NAME = 
OUTPUT = .\encrypt_and_hash_example
DEBUG_INFO = TRUE
GEN_HEX_C_FILE = FALSE
SCRATCH_BASE_ADDR = 0x00000004
SCRATCH_SIZE = 0x00003ffc
SDRAM_BASE_ADDR = 0x00000010
SDRAM_SIZE = 0x7ffffff0
SRAM_BANK0_BASE_ADDR = 0x00000004
SRAM_BANK0_SIZE = 0x03fffffc
SRAM_BANK1_BASE_ADDR = 0x00000004
SRAM_BANK1_SIZE = 0x03fffffc
SRAM_BANK2_BASE_ADDR = 0x00000004
SRAM_BANK2_SIZE = 0x03fffffc
SRAM_BANK3_BASE_ADDR = 0x00000004
SRAM_BANK3_SIZE = 0x03fffffc
GEN_SEG_H_FILE = FALSE
GEN_MEM_MAP_FILE = FALSE
MAP_FILE = .\encrypt_and_hash_example.map
# Begin Linker Map
MICROENGINE_NUMBER = 0
MICROENGINE_LIST_FILE = .\encrypt_and_hash_example.list
# End Linker Map
# End Linker Settings
# End Project