ffs.uc

网络处理器例子程序1

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/////////////////////////////////////////////////////////////////////////////////////
//
//
//	File Name: ffs.uc
//	
//	Purpose: This examples illustrates the sample round robin scheduling 
//  using ffs instruction which finds the first bit set beginning at the LSB in the 
//  Src reg.
//
//
//	History:
//
//
//	Date		Comment				By
//	----------------------------------------------------------------------------------
//	
//	10/19/2001	Created 			Minal Patel
//
//
//////////////////////////////////////////////////////////////////////////////////////
//
// ======== Pseudocode =========
// 
//  	start of the infinite loop
//			- Get the updated bit vector from external source
//  		- Do ffs on the bit vector (result in ffs_res)
//  		- if(no bit set)
//   			- reset the mask to all ones
//				- loop back to the start of the loop
//			- (Queue #0x(ffs_res) ready for scheduling)
//			- Clear the set LSB of bit_vector
//			- loop back to the start of the loop
// ==================================

//  For our example, bit_vector = A400 0002  


// code for thread 0

.if(ctx()==0) 

// register declaration

.reg bit_vector, tmp_vector, ffs_res, allone_mask, one_bit mask 

// initialization
 
	immed[bit_vector, 0x0002]					; init bit_vector
	immed_w1[bit_vector,0xa400]					; bit_vector has a bit for each queue

    immed[one_bit, 0x8000, <<16]				; init one_bit 

    immed[allone_mask,0xffffffff, <<16]			; init allone_mask 

	alu[mask, --, B, allone_mask]				; init mask to all ones


// infinite loop

loop#:

    //In the real scheduler one will get the updated bit_vector here

	alu[tmp_vector, bit_vector, AND, mask]		; tmp_vector = bit_vector AND mask

	ffs[ffs_res,tmp_vector]						; ffs on tmp_vector ,res range[0,0x1f]
    
 	BEQ[no_bit_set#]							; no bit set in bit_vector(Z=1), reset 
												; the mask 
	
	// Queue #0x(ffs_res) is ready for scheduling
	// Store this ffs_res bit for further processing if necessary
 	
	//The following three instruction are there to get the new mask
		
   	alu[ffs_res, 0x1e, -, ffs_res]  ; subtracting ffs_res from 30 (0x1e).
    
 	alu[--,ffs_res, OR, one_bit]
	// the above instr satisfies following 3 requirements of asr instr

    // the prev instr to asr should put a value in the MSB of the result
	// ORing ffs_res with one_bit sets the MSB of the result

    // >>indirect - right shifts by the amt specified in the lower 5 bits of A 
	// operand of prev instr. (A operand - ffs_res)

	// also asr requires alu_shf or alu as prev instr with either of  
	// AND, AND~,AND~, XOR, OR operators.


	asr[mask,one_bit,>>indirect]	; asr instr arithmetic right shifts the src reg,
									; replicating the MSB into vacated bit positions

	br[loop#]

no_bit_set#:
  alu[mask, --, B, allone_mask]		; reset the mask to all ones
  br[loop#]

.endif

// Code for all threads except 0

   ctx_arb[kill]				 				; kill all other threads except 0