📄 os_cpu_c.lst
字号:
68 =2 sfr SADEN0 = 0xB9; /* SERIAL PORT 0 SLAVE ADDRESS MASK */
69 =2 sfr AMX0CF = 0xBA; /* ADC 0 MUX CONFIGURATION */
70 =2 sfr AMX0SL = 0xBB; /* ADC 0 MUX CHANNEL SELECTION */
71 =2 sfr ADC0CF = 0xBC; /* ADC 0 CONFIGURATION */
72 =2 sfr P1MDIN = 0xBD; /* PORT 1 INPUT MODE */
73 =2 sfr ADC0L = 0xBE; /* ADC 0 DATA - LOW BYTE */
74 =2 sfr ADC0H = 0xBF; /* ADC 0 DATA - HIGH BYTE */
75 =2 sfr SMB0CN = 0xC0; /* SMBUS 0 CONTROL */
76 =2 sfr SMB0STA = 0xC1; /* SMBUS 0 STATUS */
77 =2 sfr SMB0DAT = 0xC2; /* SMBUS 0 DATA */
78 =2 sfr SMB0ADR = 0xC3; /* SMBUS 0 SLAVE ADDRESS */
79 =2 sfr ADC0GTL = 0xC4; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
80 =2 sfr ADC0GTH = 0xC5; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
81 =2 sfr ADC0LTL = 0xC6; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
82 =2 sfr ADC0LTH = 0xC7; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
83 =2 sfr T2CON = 0xC8; /* TIMER 2 CONTROL */
84 =2 sfr T4CON = 0xC9; /* TIMER 4 CONTROL */
85 =2 sfr RCAP2L = 0xCA; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
86 =2 sfr RCAP2H = 0xCB; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
87 =2 sfr TL2 = 0xCC; /* TIMER 2 - LOW BYTE */
88 =2 sfr TH2 = 0xCD; /* TIMER 2 - HIGH BYTE */
89 =2 sfr SMB0CR = 0xCF; /* SMBUS 0 CLOCK RATE */
90 =2 sfr PSW = 0xD0; /* PROGRAM STATUS WORD */
91 =2 sfr REF0CN = 0xD1; /* VOLTAGE REFERENCE 0 CONTROL */
92 =2 sfr DAC0L = 0xD2; /* DAC 0 REGISTER - LOW BYTE */
93 =2 sfr DAC0H = 0xD3; /* DAC 0 REGISTER - HIGH BYTE */
94 =2 sfr DAC0CN = 0xD4; /* DAC 0 CONTROL */
95 =2 sfr DAC1L = 0xD5; /* DAC 1 REGISTER - LOW BYTE */
C51 COMPILER V7.01 OS_CPU_C 02/20/2003 17:21:50 PAGE 14
96 =2 sfr DAC1H = 0xD6; /* DAC 1 REGISTER - HIGH BYTE */
97 =2 sfr DAC1CN = 0xD7; /* DAC 1 CONTROL */
98 =2 sfr PCA0CN = 0xD8; /* PCA 0 COUNTER CONTROL */
99 =2 sfr PCA0MD = 0xD9; /* PCA 0 COUNTER MODE */
100 =2 sfr PCA0CPM0 = 0xDA; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
101 =2 sfr PCA0CPM1 = 0xDB; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
102 =2 sfr PCA0CPM2 = 0xDC; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
103 =2 sfr PCA0CPM3 = 0xDD; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
104 =2 sfr PCA0CPM4 = 0xDE; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
105 =2 sfr ACC = 0xE0; /* ACCUMULATOR */
106 =2 sfr XBR0 = 0xE1; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
107 =2 sfr XBR1 = 0xE2; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
108 =2 sfr XBR2 = 0xE3; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
109 =2 sfr RCAP4L = 0xE4; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
110 =2 sfr RCAP4H = 0xE5; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
111 =2 sfr EIE1 = 0xE6; /* EXTERNAL INTERRUPT ENABLE 1 */
112 =2 sfr EIE2 = 0xE7; /* EXTERNAL INTERRUPT ENABLE 2 */
113 =2 sfr ADC0CN = 0xE8; /* ADC 0 CONTROL */
114 =2 sfr PCA0L = 0xE9; /* PCA 0 TIMER - LOW BYTE */
115 =2 sfr PCA0CPL0 = 0xEA; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
116 =2 sfr PCA0CPL1 = 0xEB; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
117 =2 sfr PCA0CPL2 = 0xEC; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
118 =2 sfr PCA0CPL3 = 0xED; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
119 =2 sfr PCA0CPL4 = 0xEE; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
120 =2 sfr RSTSRC = 0xEF; /* RESET SOURCE */
121 =2 sfr B = 0xF0; /* B REGISTER */
122 =2 sfr SCON1 = 0xF1; /* SERIAL PORT 1 CONTROL */
123 =2 sfr SBUF1 = 0xF2; /* SERAIL PORT 1 DATA */
124 =2 sfr SADDR1 = 0xF3; /* SERAIL PORT 1 */
125 =2 sfr TL4 = 0xF4; /* TIMER 4 DATA - LOW BYTE */
126 =2 sfr TH4 = 0xF5; /* TIMER 4 DATA - HIGH BYTE */
127 =2 sfr EIP1 = 0xF6; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
128 =2 sfr EIP2 = 0xF7; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
129 =2 sfr SPI0CN = 0xF8; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
130 =2 sfr PCA0H = 0xF9; /* PCA 0 TIMER - HIGH BYTE */
131 =2 sfr PCA0CPH0 = 0xFA; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
132 =2 sfr PCA0CPH1 = 0xFB; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
133 =2 sfr PCA0CPH2 = 0xFC; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
134 =2 sfr PCA0CPH3 = 0xFD; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
135 =2 sfr PCA0CPH4 = 0xFE; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
136 =2 sfr WDTCN = 0xFF; /* WATCHDOG TIMER CONTROL */
137 =2
138 =2
139 =2 /* BIT Registers */
140 =2
141 =2 /* TCON 0x88 */
142 =2 sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
143 =2 sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
144 =2 sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
145 =2 sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
146 =2 sbit IE1 = TCON ^ 3; /* EXT. INTERRUPT 1 EDGE FLAG */
147 =2 sbit IT1 = TCON ^ 2; /* EXT. INTERRUPT 1 TYPE */
148 =2 sbit IE0 = TCON ^ 1; /* EXT. INTERRUPT 0 EDGE FLAG */
149 =2 sbit IT0 = TCON ^ 0; /* EXT. INTERRUPT 0 TYPE */
150 =2
151 =2 /* SCON0 0x98 */
152 =2 sbit SM00 = SCON0 ^ 7; /* SERIAL MODE CONTROL BIT 0 */
153 =2 sbit SM10 = SCON0 ^ 6; /* SERIAL MODE CONTROL BIT 1 */
154 =2 sbit SM20 = SCON0 ^ 5; /* MULTIPROCESSOR COMMUNICATION ENABLE */
155 =2 sbit REN0 = SCON0 ^ 4; /* RECEIVE ENABLE */
156 =2 sbit TB80 = SCON0 ^ 3; /* TRANSMIT BIT 8 */
157 =2 sbit RB80 = SCON0 ^ 2; /* RECEIVE BIT 8 */
C51 COMPILER V7.01 OS_CPU_C 02/20/2003 17:21:50 PAGE 15
158 =2 sbit TI0 = SCON0 ^ 1; /* TRANSMIT INTERRUPT FLAG */
159 =2 sbit RI0 = SCON0 ^ 0; /* RECEIVE INTERRUPT FLAG */
160 =2 /* p0*/
161 =2 sbit P00 = 0x80;
162 =2 sbit P01 = 0x81;
163 =2 sbit P02 = 0x82;
164 =2 sbit P03 = 0x83;
165 =2 sbit P04 = 0x84;
166 =2 sbit P05 = 0x85;
167 =2 sbit P06 = 0x86;
168 =2 sbit P07 = 0x87;
169 =2 /* p1*/
170 =2 sbit P10 = 0x90;
171 =2 sbit P11 = 0x91;
172 =2 sbit P12 = 0x92;
173 =2 sbit P13 = 0x93;
174 =2 sbit P14 = 0x94;
175 =2 sbit P15 = 0x95;
176 =2 sbit P16 = 0x96;
177 =2 sbit P17 = 0x97;
178 =2 /* p2*/
179 =2 sbit P20 = 0xa0;
180 =2 sbit P21 = 0xa1;
181 =2 sbit P22 = 0xa2;
182 =2 sbit P23 = 0xa3;
183 =2 sbit P24 = 0xa4;
184 =2 sbit P25 = 0xa5;
185 =2 sbit P26 = 0xa6;
186 =2 sbit P27 = 0xa7;
187 =2 /* p3*/
188 =2 sbit P30 = 0xb0;
189 =2 sbit P31 = 0xb1;
190 =2 sbit P32 = 0xb2;
191 =2 sbit P33 = 0xb3;
192 =2 sbit P34 = 0xb4;
193 =2 sbit P35 = 0xb5;
194 =2 sbit P36 = 0xb6;
195 =2 sbit P37 = 0xb7;
196 =2
197 =2
198 =2 /* IE 0xA8 */
199 =2 sbit EA = IE ^ 7; /* GLOBAL INTERRUPT ENABLE */
200 =2 sbit ET2 = IE ^ 5; /* TIMER 2 INTERRUPT ENABLE */
201 =2 sbit ES0 = IE ^ 4; /* UART0 INTERRUPT ENABLE */
202 =2 sbit ET1 = IE ^ 3; /* TIMER 1 INTERRUPT ENABLE */
203 =2 sbit EX1 = IE ^ 2; /* EXTERNAL INTERRUPT 1 ENABLE */
204 =2 sbit ET0 = IE ^ 1; /* TIMER 0 INTERRUPT ENABLE */
205 =2 sbit EX0 = IE ^ 0; /* EXTERNAL INTERRUPT 0 ENABLE */
206 =2
207 =2 /* IP 0xB8 */
208 =2 sbit PT2 = IP ^ 5; /* TIMER 2 PRIORITY */
209 =2 sbit PS = IP ^ 4; /* SERIAL PORT PRIORITY */
210 =2 sbit PT1 = IP ^ 3; /* TIMER 1 PRIORITY */
211 =2 sbit PX1 = IP ^ 2; /* EXTERNAL INTERRUPT 1 PRIORITY */
212 =2 sbit PT0 = IP ^ 1; /* TIMER 0 PRIORITY */
213 =2 sbit PX0 = IP ^ 0; /* EXTERNAL INTERRUPT 0 PRIORITY */
214 =2
215 =2 /* SMB0CN 0xC0 */
216 =2 sbit BUSY = SMB0CN ^ 7; /* SMBUS 0 BUSY */
217 =2 sbit ENSMB = SMB0CN ^ 6; /* SMBUS 0 ENABLE */
218 =2 sbit STA = SMB0CN ^ 5; /* SMBUS 0 START FLAG */
219 =2 sbit STO = SMB0CN ^ 4; /* SMBUS 0 STOP FLAG */
C51 COMPILER V7.01 OS_CPU_C 02/20/2003 17:21:50 PAGE 16
220 =2 sbit SI = SMB0CN ^ 3; /* SMBUS 0 INTERRUPT PENDING FLAG */
221 =2 sbit AA = SMB0CN ^ 2; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
222 =2 sbit SMBFTE = SMB0CN ^ 1; /* SMBUS 0 FREE TIMER ENABLE */
223 =2 sbit SMBTOE = SMB0CN ^ 0; /* SMBUS 0 TIMEOUT ENABLE */
224 =2
225 =2 /* T2CON 0xC8 */
226 =2 sbit TF2 = T2CON ^ 7; /* TIMER 2 OVERFLOW FLAG */
227 =2 sbit EXF2 = T2CON ^ 6; /* EXTERNAL FLAG */
228 =2 sbit RCLK = T2CON ^ 5; /* RECEIVE CLOCK FLAG */
229 =2 sbit TCLK = T2CON ^ 4; /* TRANSMIT CLOCK FLAG */
230 =2 sbit EXEN2 = T2CON ^ 3; /* TIMER 2 EXTERNAL ENABLE FLAG */
231 =2 sbit TR2 = T2CON ^ 2; /* TIMER 2 ON/OFF CONTROL */
232 =2 sbit CT2 = T2CON ^ 1; /* TIMER OR COUNTER SELECT */
233 =2 sbit CPRL2 = T2CON ^ 0; /* CAPTURE OR RELOAD SELECT */
234 =2
235 =2 /* PSW */
236 =2 sbit CY = PSW ^ 7; /* CARRY FLAG */
237 =2 sbit AC = PSW ^ 6; /* AUXILIARY CARRY FLAG */
238 =2 sbit F0 = PSW ^ 5; /* USER FLAG 0 */
239 =2 sbit RS1 = PSW ^ 4; /* REGISTER BANK SELECT 1 */
240 =2 sbit RS0 = PSW ^ 3; /* REGISTER BANK SELECT 0 */
241 =2 sbit OV = PSW ^ 2; /* OVERFLOW FLAG */
242 =2 sbit F1 = PSW ^ 1; /* USER FLAG 1 */
243 =2 sbit P = PSW ^ 0; /* ACCUMULATOR PARITY FLAG */
244 =2
245 =2 /* PCA0CN D8H */
246 =2 sbit CF = PCA0CN ^ 7; /* PCA 0 COUNTER OVERFLOW FLAG */
247 =2 sbit CR = PCA0CN ^ 6; /* PCA 0 COUNTER RUN CONTROL BIT */
248 =2 sbit CCF4 = PCA0CN ^ 4; /* PCA 0 MODULE 4 INTERRUPT FLAG */
249 =2 sbit CCF3 = PCA0CN ^ 3; /* PCA 0 MODULE 3 INTERRUPT FLAG */
250 =2 sbit CCF2 = PCA0CN ^ 2; /* PCA 0 MODULE 2 INTERRUPT FLAG */
251 =2 sbit CCF1 = PCA0CN ^ 1; /* PCA 0 MODULE 1 INTERRUPT FLAG */
252 =2 sbit CCF0 = PCA0CN ^ 0; /* PCA 0 MODULE 0 INTERRUPT FLAG */
253 =2
254 =2 /* ADC0CN E8H */
255 =2 sbit AD0EN = ADC0CN ^ 7; /* ADC 0 ENABLE */
256 =2 sbit AD0TM = ADC0CN ^ 6; /* ADC 0 TRACK MODE */
257 =2 sbit AD0INT = ADC0CN ^ 5; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
258 =2 sbit AD0BUSY = ADC0CN ^ 4; /* ADC 0 BUSY FLAG */
259 =2 sbit AD0CM1 = ADC0CN ^ 3; /* ADC 0 START OF CONVERSION MODE BIT 1 */
260 =2 sbit AD0CM0 = ADC0CN ^ 2; /* ADC 0 START OF CONVERSION MODE BIT 0 */
261 =2 sbit AD0WINT = ADC0⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -