dma_fun.c

ARM9摄象头驱动程序

/**********************

	MX1 DMA driver

**********************/

static U32 DMA_ModuleInitDone = 0;

//
//      Enable DMA module
//
void DMA_module_enable(void)
{
	*(U32 *) DMA_DCR |= 0x1;
	return;
}


//
//      Reset DMA module
//
void DMA_module_reset(void)
{
	*(U32 *) DMA_DCR |= 0x2;
	return;
}


//
//      Module Init
//
static void DMA_ModuleInit(void)
{
	DMA_module_reset();
	DMA_module_enable();
	DMA_ModuleInitDone = 1;
}

//
//      Check DMA finished ?
//
U32 DMA_poll(U32 channel)
{
	//check interrupt pending bits
	if (*(U32 *) DMA_ISR & (0x1 << channel)) {
		*(U32 *) DMA_ISR = (0x1 << channel);	//clear pending
		return 1;
	} else
		return 0;
}


//
//      Enable DMA channel
//
void DMA_channel_enable(U32 channel)
{
	*(U32 *) (DMA_CCR0 + (0x40 * channel)) |= 0x1;
	return;
}


//
//      Disable DMA channel
//
void DMA_channel_disable(U32 channel)
{
	*(U32 *) (DMA_CCR0 + (0x40 * channel)) &= ~0x1;
	return;
}


//
//      Re-enable DMA channel
//
void DMA_ChannelReEnable(U32 channel)
{
	*(U32 *) (DMA_CCR0 + (0x40 * channel)) &= ~0x1;
	*(U32 *) (DMA_CCR0 + (0x40 * channel)) |= 0x1;
	return;
}


//
//      DMA driver
//      FIFO to 1D Window
//
void
DMA_init(U32 Ch, U32 BurstLen, U32 Src, U32 ByteCount, U32 Dest,
	 U32 ReqSrc, U32 Rpt)
{
	if (!DMA_ModuleInitDone)
		DMA_ModuleInit();

	//assign pointers
	*(U32 *) (DMA_SAR0 + (0x40 * Ch)) = Src;
	*(U32 *) (DMA_DAR0 + (0x40 * Ch)) = Dest;

	//transfer control
	*(U32 *) (DMA_BLR0 + (0x40 * Ch)) = BurstLen;	//burst control
	*(U32 *) (DMA_CNTR0 + (0x40 * Ch)) = ByteCount;	//no. of BYTE to be transferred
	*(U32 *) DMA_IMR |= (0x1 << Ch);	//IRQ disable

	//channel control
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) = 0x0;	//clear register
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x8;	//DMA req enable
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x0800;	//source = FIFO
	if (Rpt)
		*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x0004;	//repeat
	*(U32 *) (DMA_RSSR0 + (0x40 * Ch)) = ReqSrc;	//setup req no.

	//bus ultilization control (wait state between burst)
	*(U32 *) (DMA_BUCR0 + (0x40 * Ch)) = 4;

	return;
}



//
//      DMA driver
//      Memory 1D to 1D
//
void
DMA_init1(U32 Ch, U32 BurstLen, U32 Src, U32 ByteCount, U32 Dest, U32 Rpt)
{
	if (!DMA_ModuleInitDone)
		DMA_ModuleInit();

	//assign pointers
	*(U32 *) (DMA_SAR0 + (0x40 * Ch)) = Src;
	*(U32 *) (DMA_DAR0 + (0x40 * Ch)) = Dest;

	//transfer control
	*(U32 *) (DMA_BLR0 + (0x40 * Ch)) = BurstLen;	//burst control
	*(U32 *) (DMA_CNTR0 + (0x40 * Ch)) = ByteCount;	//no. of BYTE to be transferred
	*(U32 *) DMA_IMR |= (0x1 << Ch);	//IRQ disable

	//channel control
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) = 0x0;	//clear register
	if (Rpt)
		*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x0004;	//repeat

	//bus ultilization control (wait state between burst)
	*(U32 *) (DMA_BUCR0 + (0x40 * Ch)) = 128;

	return;
}



//
//      DMA driver
//      FIFO to 2D Window
//      160 x 120 to 240 x 320
//
void
DMA_init2(U32 Ch, U32 BurstLen, U32 Src, U32 ByteCount, U32 Dest,
	  U32 ReqSrc, U32 Rpt)
{
	if (!DMA_ModuleInitDone)
		DMA_ModuleInit();

	//assign pointers
	*(U32 *) (DMA_SAR0 + (0x40 * Ch)) = Src;
	*(U32 *) (DMA_DAR0 + (0x40 * Ch)) = Dest;

	//transfer control
	*(U32 *) (DMA_BLR0 + (0x40 * Ch)) = BurstLen;	//burst control
	*(U32 *) (DMA_CNTR0 + (0x40 * Ch)) = ByteCount;	//no. of BYTE to be transferred
	*(U32 *) DMA_IMR |= (0x1 << Ch);	//IRQ disable

	//2D control (set A)
	*(U32 *) (DMA_WSRA) = 480;	//240 x 2
	*(U32 *) (DMA_XSRA) = 320;	//160 x 2
	*(U32 *) (DMA_YSRA) = 120;

	//channel control
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) = 0x0;	//clear register
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x8;	//DMA req enable
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x0800;	//source = FIFO
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x1000;	//dest = 2D
	if (Rpt)
		*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x0004;	//repeat
	*(U32 *) (DMA_RSSR0 + (0x40 * Ch)) = ReqSrc;	//setup req no.

	//bus ultilization control (wait state between burst)
	*(U32 *) (DMA_BUCR0 + (0x40 * Ch)) = 4;

	return;
}


//
//      DMA driver
//      2D to 2D Window
//      320 x 240 to 240 x 240
//
void DMA_init3(U32 Ch, U32 BurstLen, U32 Src, U32 Dest, U32 Rpt)
{
	if (!DMA_ModuleInitDone)
		DMA_ModuleInit();

	//assign pointers
	*(U32 *) (DMA_SAR0 + (0x40 * Ch)) = Src;
	*(U32 *) (DMA_DAR0 + (0x40 * Ch)) = Dest;

	//transfer control
	*(U32 *) (DMA_BLR0 + (0x40 * Ch)) = BurstLen;	//burst control
	*(U32 *) (DMA_CNTR0 + (0x40 * Ch)) = 115200;	//240 x 240 x 2 bytes
	*(U32 *) DMA_IMR |= (0x1 << Ch);	//IRQ disable

	//2D control (set A)
	*(U32 *) (DMA_WSRA) = 640;	//320 x 2
	*(U32 *) (DMA_XSRA) = 480;	//240 x 2
	*(U32 *) (DMA_YSRA) = 240;

	//channel control
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) = 0x0;	//clear register
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x400;	//src = 2D
	if (Rpt)
		*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x0004;	//repeat

	//bus ultilization control (wait state between burst)
	*(U32 *) (DMA_BUCR0 + (0x40 * Ch)) = 128;

	return;
}




//
//      DMA driver
//      2D to 2D Window
//      640 x 480 to 240 x 320
//
void DMA_init4(U32 Ch, U32 BurstLen, U32 Src, U32 Dest, U32 Rpt)
{
	if (!DMA_ModuleInitDone)
		DMA_ModuleInit();

	//assign pointers
	*(U32 *) (DMA_SAR0 + (0x40 * Ch)) = Src;
	*(U32 *) (DMA_DAR0 + (0x40 * Ch)) = Dest;

	//transfer control
	*(U32 *) (DMA_BLR0 + (0x40 * Ch)) = BurstLen;	//burst control
	*(U32 *) (DMA_CNTR0 + (0x40 * Ch)) = 115200;	//240 x 240 x 2 bytes
	*(U32 *) DMA_IMR |= (0x1 << Ch);	//IRQ disable

	//2D control (set A)
	*(U32 *) (DMA_WSRA) = 1280;	//320 x 2
	*(U32 *) (DMA_XSRA) = 480;	//240 x 2
	*(U32 *) (DMA_YSRA) = 320;

	//channel control
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) = 0x0;	//clear register
	*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x400;	//src = 2D
	if (Rpt)
		*(U32 *) (DMA_CCR0 + (0x40 * Ch)) |= 0x0004;	//repeat

	//bus ultilization control (wait state between burst)
	*(U32 *) (DMA_BUCR0 + (0x40 * Ch)) = 128;

	return;
}