📄 mx1hw.h
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#define RTC_SECOND (RTC_BASE_ADDR+0x04)#define RTC_ALRM_HM (RTC_BASE_ADDR+0x08)#define RTC_ALRM_SEC (RTC_BASE_ADDR+0x0C)#define RTC_RTCCTL (RTC_BASE_ADDR+0x10)#define RTC_RTCISR (RTC_BASE_ADDR+0x14)#define RTC_RTCIENR (RTC_BASE_ADDR+0x18)#define RTC_STPWCH (RTC_BASE_ADDR+0x1C)#define RTC_DAYR (RTC_BASE_ADDR+0x20)#define RTC_DAYALARM (RTC_BASE_ADDR+0x24)#define RTC_TEST1 (RTC_BASE_ADDR+0x28)#define RTC_TEST2 (RTC_BASE_ADDR+0x2C)#define RTC_TEST3 (RTC_BASE_ADDR+0x30)//// ;---------------------------------------;// ; SRAMC ;// ; $0022_1000 to $0022_1FFF ;// ;---------------------------------------;#define SDRAMC_BASE_ADDR 0x00221000#define SDRAMC_SDCTL0 SDRAMC_BASE_ADDR#define SDRAMC_SDCTL1 (SDRAMC_BASE_ADDR+0x04)//// ;---------------------------------------;// ; SIM ;// ; $0021_1000 to $0021_21FF ;// ;---------------------------------------;#define SIM_BASE_ADDR 0x00211000#define SIM_PORT_CNTL SIM_BASE_ADDR#define SIM_CNTL SIM_BASE_ADDR+0x04)#define SIM_RCV_THRESHOLD SIM_BASE_ADDR+0x08)#define SIM_ENABLE SIM_BASE_ADDR+0x0C)#define SIM_XMT_STATUS (SIM_BASE_ADDR+0x10)#define SIM_RCV_STATUS (SIM_BASE_ADDR+0x14)#define SIM_INT_MASK (SIM_BASE_ADDR+0x18)#define SIM_PORT_XMT_BUF (SIM_BASE_ADDR+0x1C)#define SIM_PORT_RCV_BUF (SIM_BASE_ADDR+0x20)#define SIM_PORT_DETECT (SIM_BASE_ADDR+0x24)#define SIM_XMT_THRESHOLD (SIM_BASE_ADDR+0x28)#define SIM_GUARD_CNTL (SIM_BASE_ADDR+0x2C)#define SIM_OD_CONFIG (SIM_BASE_ADDR+0x30)#define SIM_RESET_CNTL (SIM_BASE_ADDR+0x34)#define SIM_CHAR_WAIT (SIM_BASE_ADDR+0x38)#define SIM_GPCNT (SIM_BASE_ADDR+0x3C)#define SIM_DIVISOR (SIM_BASE_ADDR+0x40)//// ;---------------------------------------;// ; TIMER1 ;// ; $0020_2000 to $0020_2FFF ;// ;---------------------------------------;#define TIMER1_BASE_ADDR 0x00202000#define TIMER1_TCTL1 TIMER1_BASE_ADDR#define TIMER1_TPRER1 (TIMER1_BASE_ADDR+0x04)#define TIMER1_TCMP1 (TIMER1_BASE_ADDR+0x08)#define TIMER1_TCR1 (TIMER1_BASE_ADDR+0x0C)#define TIMER1_TCN1 (TIMER1_BASE_ADDR+0x10)#define TIMER1_TSTAT1 (TIMER1_BASE_ADDR+0x14)// ;---------------------------------------;// ; TIMER2 ;// ; $0020_3000 to $0020_3FFF ;// ;---------------------------------------;#define TIMER2_BASE_ADDR 0x00203000#define TIMER2_TCTL2 TIMER2_BASE_ADDR#define TIMER2_TPRER2 (TIMER2_BASE_ADDR+0x04)#define TIMER2_TCMP2 (TIMER2_BASE_ADDR+0x08)#define TIMER2_TCR2 (TIMER2_BASE_ADDR+0x0C)#define TIMER2_TCN2 (TIMER2_BASE_ADDR+0x10)#define TIMER2_TSTAT2 (TIMER2_BASE_ADDR+0x14)//// ;---------------------------------------;// ; TUBE ;// ; CS5 address space ;// ; $1600_0000 to $16FF_FFFF ;// ;---------------------------------------;#define TubeBase 0x16000000#define TUBEDataOff 0 // ; Register offsets#define TUBEDataMask 15 // ; Data#define CR 13 // ;Carriage return char#define LF 10 // ;Line Feed char#define CTRLD 4 // ;Control D char//// ;---------------------------------------;// ; UART1 ;// ; $0020_6000 to $0020_6FFF ;// ;---------------------------------------;#define UART1_BASE_ADDR 0x00206000#define UART1_RXDATA UART1_BASE_ADDR#define UART1_TXDATA (UART1_BASE_ADDR+0x40)#define UART1_CR1 (UART1_BASE_ADDR+0x80)#define UART1_CR2 (UART1_BASE_ADDR+0x84)#define UART1_CR3 (UART1_BASE_ADDR+0x88)#define UART1_CR4 (UART1_BASE_ADDR+0x8C)#define UART1_FCR (UART1_BASE_ADDR+0x90)#define UART1_SR1 (UART1_BASE_ADDR+0x94)#define UART1_SR2 (UART1_BASE_ADDR+0x98)#define UART1_ESC (UART1_BASE_ADDR+0x9C)#define UART1_TIM (UART1_BASE_ADDR+0xA0)#define UART1_BIR (UART1_BASE_ADDR+0xA4)#define UART1_BMR (UART1_BASE_ADDR+0xA8)#define UART1_BRC (UART1_BASE_ADDR+0xAC)#define UART1_BIPR1 (UART1_BASE_ADDR+0xB0)#define UART1_BMPR1 (UART1_BASE_ADDR+0xB4)#define UART1_BIPR2 (UART1_BASE_ADDR+0xB8)#define UART1_BMPR2 (UART1_BASE_ADDR+0xBC)#define UART1_BIPR3 (UART1_BASE_ADDR+0xC0)#define UART1_BMPR3 (UART1_BASE_ADDR+0xC4)#define UART1_BIPR4 (UART1_BASE_ADDR+0xC8)#define UART1_BMPR4 (UART1_BASE_ADDR+0xCC)#define UART1_TS (UART1_BASE_ADDR+0xD0)//// ;---------------------------------------;// ; UART2 ;// ; $0020_7000 to $0020_7FFF ;// ;---------------------------------------;#define UART2_BASE_ADDR 0x00207000#define UART2_RXDATA UART2_BASE_ADDR#define UART2_TXDATA (UART2_BASE_ADDR+0x40)#define UART2_CR1 (UART2_BASE_ADDR+0x80)#define UART2_CR2 (UART2_BASE_ADDR+0x84)#define UART2_CR3 (UART2_BASE_ADDR+0x88)#define UART2_CR4 (UART2_BASE_ADDR+0x8C)#define UART2_FCR (UART2_BASE_ADDR+0x90)#define UART2_SR1 (UART2_BASE_ADDR+0x94)#define UART2_SR2 (UART2_BASE_ADDR+0x98)#define UART2_ESC (UART2_BASE_ADDR+0x9C)#define UART2_TIM (UART2_BASE_ADDR+0xA0)#define UART2_BIR (UART2_BASE_ADDR+0xA4)#define UART2_BMR (UART2_BASE_ADDR+0xA8)#define UART2_BRC (UART2_BASE_ADDR+0xAC)#define UART2_BIPR1 (UART2_BASE_ADDR+0xB0)#define UART2_BMPR1 (UART2_BASE_ADDR+0xB4)#define UART2_BIPR2 (UART2_BASE_ADDR+0xB8)#define UART2_BMPR2 (UART2_BASE_ADDR+0xBC)#define UART2_BIPR3 (UART2_BASE_ADDR+0xC0)#define UART2_BMPR3 (UART2_BASE_ADDR+0xC4)#define UART2_BIPR4 (UART2_BASE_ADDR+0xC8)#define UART2_BMPR4 (UART2_BASE_ADDR+0xCC)#define UART2_TS (UART2_BASE_ADDR+0xD0)// ;---------------------------------------;// ; USBD ;// ; $0021_2000 to $0021_2FFF ;// ;---------------------------------------;#define USBD_BASE_ADDR 0x00212000#define USBD_FRAME USBD_BASE_ADDR#define USBD_SPEC (USBD_BASE_ADDR+0x04)#define USBD_STAT (USBD_BASE_ADDR+0x08)#define USBD_CTRL (USBD_BASE_ADDR+0x0C)#define USBD_DADR (USBD_BASE_ADDR+0x10)#define USBD_DDAT (USBD_BASE_ADDR+0x14)#define USBD_INTR (USBD_BASE_ADDR+0x18)#define USBD_MASK (USBD_BASE_ADDR+0x1C)#define USBD_MCTL (USBD_BASE_ADDR+0x20)#define USBD_ENABLE (USBD_BASE_ADDR+0x24)//#define USBD_EP0_STAT (USBD_BASE_ADDR+0x30)#define USBD_EP0_INTR (USBD_BASE_ADDR+0x34)#define USBD_EP0_MASK (USBD_BASE_ADDR+0x38)#define USBD_EP0_FDAT (USBD_BASE_ADDR+0x3C)#define USBD_EP0_FSTAT (USBD_BASE_ADDR+0x40)#define USBD_EP0_FCTRL (USBD_BASE_ADDR+0x44)#define USBD_EP0_LFRP (USBD_BASE_ADDR+0x48)#define USBD_EP0_LFWP (USBD_BASE_ADDR+0x4C)#define USBD_EP0_FALRM (USBD_BASE_ADDR+0x50)#define USBD_EP0_FRDP (USBD_BASE_ADDR+0x54)#define USBD_EP0_FWDP (USBD_BASE_ADDR+0x58)//#define USBD_EP1_STAT (USBD_BASE_ADDR+0x60)#define USBD_EP1_INTR (USBD_BASE_ADDR+0x64)#define USBD_EP1_MASK (USBD_BASE_ADDR+0x68)#define USBD_EP1_FDAT (USBD_BASE_ADDR+0x6C)#define USBD_EP1_FSTAT (USBD_BASE_ADDR+0x70)#define USBD_EP1_FCTRL (USBD_BASE_ADDR+0x74)#define USBD_EP1_LFRP (USBD_BASE_ADDR+0x78)#define USBD_EP1_LFWP (USBD_BASE_ADDR+0x7C)#define USBD_EP1_FALRM (USBD_BASE_ADDR+0x80)#define USBD_EP1_FRDP (USBD_BASE_ADDR+0x84)#define USBD_EP1_FWDP (USBD_BASE_ADDR+0x88)//#define USBD_EP2_STAT (USBD_BASE_ADDR+0x90)#define USBD_EP2_INTR (USBD_BASE_ADDR+0x94)#define USBD_EP2_MASK (USBD_BASE_ADDR+0x98)#define USBD_EP2_FDAT (USBD_BASE_ADDR+0x9C)#define USBD_EP2_FSTAT (USBD_BASE_ADDR+0xA0)#define USBD_EP2_FCTRL (USBD_BASE_ADDR+0xA4)#define USBD_EP2_LFRP (USBD_BASE_ADDR+0xA8)#define USBD_EP2_LFWP (USBD_BASE_ADDR+0xAC)#define USBD_EP2_FALRM (USBD_BASE_ADDR+0xB0)#define USBD_EP2_FRDP (USBD_BASE_ADDR+0xB4)#define USBD_EP2_FWDP (USBD_BASE_ADDR+0xB8)// #define USBD_EP3_STAT (USBD_BASE_ADDR+0xC0)#define USBD_EP3_INTR (USBD_BASE_ADDR+0xC4)#define USBD_EP3_MASK (USBD_BASE_ADDR+0xC8)#define USBD_EP3_FDAT (USBD_BASE_ADDR+0xCC)#define USBD_EP3_FSTAT (USBD_BASE_ADDR+0xD0)#define USBD_EP3_FCTRL (USBD_BASE_ADDR+0xD4)#define USBD_EP3_LFRP (USBD_BASE_ADDR+0xD8)#define USBD_EP3_LFWP (USBD_BASE_ADDR+0xDC)#define USBD_EP3_FALRM (USBD_BASE_ADDR+0xE0)#define USBD_EP3_FRDP (USBD_BASE_ADDR+0xE4)#define USBD_EP3_FWDP (USBD_BASE_ADDR+0xE8)//#define USBD_EP4_STAT (USBD_BASE_ADDR+0xF0)#define USBD_EP4_INTR (USBD_BASE_ADDR+0xF4)#define USBD_EP4_MASK (USBD_BASE_ADDR+0xF8)#define USBD_EP4_FDAT (USBD_BASE_ADDR+0xFC)#define USBD_EP4_FSTAT (USBD_BASE_ADDR+0x100)#define USBD_EP4_FCTRL (USBD_BASE_ADDR+0x104)#define USBD_EP4_LFRP (USBD_BASE_ADDR+0x108)#define USBD_EP4_LFWP (USBD_BASE_ADDR+0x10C)#define USBD_EP4_FALRM (USBD_BASE_ADDR+0x110)#define USBD_EP4_FRDP (USBD_BASE_ADDR+0x114)#define USBD_EP4_FWDP (USBD_BASE_ADDR+0x118)#define USBD_EP5_STAT (USBD_BASE_ADDR+0x120)#define USBD_EP5_INTR (USBD_BASE_ADDR+0x124)#define USBD_EP5_MASK (USBD_BASE_ADDR+0x128)#define USBD_EP5_FDAT (USBD_BASE_ADDR+0x12C)#define USBD_EP5_FSTAT (USBD_BASE_ADDR+0x130)#define USBD_EP5_FCTRL (USBD_BASE_ADDR+0x134)#define USBD_EP5_LFRP (USBD_BASE_ADDR+0x138)#define USBD_EP5_LFWP (USBD_BASE_ADDR+0x13C)#define USBD_EP5_FALRM (USBD_BASE_ADDR+0x140)#define USBD_EP5_FRDP (USBD_BASE_ADDR+0x144)#define USBD_EP5_FWDP (USBD_BASE_ADDR+0x148)//// ;---------------------------------------;// ; CSPI_2 ;// ; $0021_9000 to $0021_9FFF ;// ;---------------------------------------;#define CSPI_2_BASE_ADDR 0x00219000#define CSPI_2_SPIRXD CSPI_2_BASE_ADDR#define CSPI_2_SPITXD (CSPI_2_BASE_ADDR+0x04)#define CSPI_2_SPICONT1 (CSPI_2_BASE_ADDR+0x08)#define CSPI_2_INTCS (CSPI_2_BASE_ADDR+0x0C)#define CSPI_2_SPITEST (CSPI_2_BASE_ADDR+0x10)#define CSPI_2_SPISPCR (CSPI_2_BASE_ADDR+0x14)#define CSPI_2_SPIDMA (CSPI_2_BASE_ADDR+0x18)#define CSPI_2_SPIRESET (CSPI_2_BASE_ADDR+0x1C)//// ;---------------------------------------;// ; WDT ;// ; $0020_1000 to $0020_1FFF ;// ;---------------------------------------;#define WDOG_BASE_ADDR 0x00201000#define WDOG_WCR WDOG_BASE_ADDR#define WDOG_WSR (WDOG_BASE_ADDR+0x04)#define WDOG_WSTR (WDOG_BASE_ADDR+0x08)// ;---------------------------------------;// ; WEIM ;// ; $0022_0000 to $0022_0FFF ;// ;---------------------------------------;#define EIM_BASE_ADDR 0x00220000#define EIM_CS0H EIM_BASE_ADDR#define EIM_CS0L (EIM_BASE_ADDR+0x04)#define EIM_CS1H (EIM_BASE_ADDR+0x08)#define EIM_CS1L (EIM_BASE_ADDR+0x0C)#define EIM_CS2H (EIM_BASE_ADDR+0x10)#define EIM_CS2L (EIM_BASE_ADDR+0x14)#define EIM_CS3H (EIM_BASE_ADDR+0x18)#define EIM_CS3L (EIM_BASE_ADDR+0x1C)#define EIM_CS4H (EIM_BASE_ADDR+0x20)#define EIM_CS4L (EIM_BASE_ADDR+0x24)#define EIM_CS5H (EIM_BASE_ADDR+0x28)#define EIM_CS5L (EIM_BASE_ADDR+0x2C)#define EIM (EIM_BASE_ADDR+0x30)//// ;---------------------------------------;// ; WEIM ;// ; $0022_0000 to $0022_0FFF ;// ;---------------------------------------;// ; External Memory address (64M Bytes each)// ;#define CSD0_BASE_ADDR 0x08000000 // ; SDRAM#define CSD0_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF)#define CSD1_BASE_ADDR 0x0C000000 // ; SDRAM#define CSD1_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF)#define CS0_BASE_ADDR 0x10000000 // ; CS0#define CS0_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF)#define CS1_BASE_ADDR 0x12000000 // ; CS1#define CS1_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF)#define CS2_BASE_ADDR 0x13000000 // ; CS2#define CS2_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF)#define CS3_BASE_ADDR 0x14000000 // ; CS3#define CS3_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF)#define CS4_BASE_ADDR 0x15000000 // ; CS4#define CS4_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF)#define CS5_BASE_ADDR 0x16000000 // ; CS5#define CS5_END_ADDR (CSD0_BASE_ADDR+0x3FFFFFF)//// ;---------------------------------------;// ; SDRAMC ;// ; $0022_0000 to $0022_0FFF ;// ;---------------------------------------;//#define SDRAM0_BASE 0x08000000#define SDRAM1_BASE 0x0C000000#define SDRAM0_END_ADDR 0x08FFFF00#define SDRAM1_END_ADDR 0x0CFFFF00//-------------------------------//// System control////-------------------------------#define GPCR (U32 *) 0x21B80C //global control register#define PCDR (U32 *) 0x21B020 //peripheral clock divider register#define CSCR (U32 *) 0x21B000 //clock source control register#endif⌨️ 快捷键说明
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