📄 mx1hw.h
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#define DSPA_MAC_ACCU (DSPA_BASE_ADDR+0x000C)#define DSPA_MAC_INTR (DSPA_BASE_ADDR+0x0010)#define DSPA_MAC_INTR_MASK (DSPA_BASE_ADDR+0x0014)#define DSPA_MAC_FIFO (DSPA_BASE_ADDR+0x0018)#define DSPA_MAC_FIFO_STAT (DSPA_BASE_ADDR+0x001C)#define DSPA_MAC_BURST (DSPA_BASE_ADDR+0x0020)#define DSPA_MAC_BIT_SEL (DSPA_BASE_ADDR+0x0024)//#define DSPA_MAC_XBASE (DSPA_BASE_ADDR+0x0200)#define DSPA_MAC_XINDEX (DSPA_BASE_ADDR+0x0204)#define DSPA_MAC_XLENGTH (DSPA_BASE_ADDR+0x0208)#define DSPA_MAC_XMODIFY (DSPA_BASE_ADDR+0x020C)#define DSPA_MAC_XINCR (DSPA_BASE_ADDR+0x0210)#define DSPA_MAC_XCOUNT (DSPA_BASE_ADDR+0x0214)//#define DSPA_MAC_YBASE (DSPA_BASE_ADDR+0x0300)#define DSPA_MAC_YINDEX (DSPA_BASE_ADDR+0x0304)#define DSPA_MAC_YLENGTH (DSPA_BASE_ADDR+0x0308)#define DSPA_MAC_YMODIFY (DSPA_BASE_ADDR+0x030C)#define DSPA_MAC_YINCR (DSPA_BASE_ADDR+0x0310)#define DSPA_MAC_YCOUNT (DSPA_BASE_ADDR+0x0314)//#define DSPA_DCTCTRL (DSPA_BASE_ADDR+0x0400)#define DSPA_DCTVER (DSPA_BASE_ADDR+0x0404)#define DSPA_DCTIRQENA (DSPA_BASE_ADDR+0x0408)#define DSPA_DCTIRQSTAT (DSPA_BASE_ADDR+0x040C)#define DSPA_DCTSRCADD (DSPA_BASE_ADDR+0x0410)#define DSPA_DCTDESADD (DSPA_BASE_ADDR+0x0414)#define DSPA_DCTFIFO (DSPA_BASE_ADDR+0x0500)//// ;---------------------------------------;// ; ESRAM ;// ; $0030_D000 to $0031_FFFF ;// ;---------------------------------------;#define eSRAM_ADDR_BOT 0x00300000 // ; Bottom of eSRAM#define eSRAM_ADDR_TOP 0x00319000 // ; Top of physical eSRAM#define eSRAM_ADDR_LMT 0x003FFFFF // ; Limit of allocated eSRAM#define eSRAM_PHY_SIZE 0x00018000 // ; Physical size of eSRAM (96k)#define eSRAM_ASS_SIZE 0x00100000 // ; Assigned size of eSRAM (1M)#define eSRAM_8K_SIZE 0x00008000 // ; 8k byte size for boundary between RAM1 & RAM2//// ;---------------------------------------;// ; GPIO - PTA ;// ; $0021_C000 to $0021_C0FF ;// ;---------------------------------------;#define PTA_BASE_ADDR 0xF021C000#define PTA_DDIR PTA_BASE_ADDR#define PTA_OCR1 (PTA_BASE_ADDR+0x04)#define PTA_OCR2 (PTA_BASE_ADDR+0x08)#define PTA_ICONFA1 (PTA_BASE_ADDR+0x0C)#define PTA_ICONFA2 (PTA_BASE_ADDR+0x10)#define PTA_ICONFB1 (PTA_BASE_ADDR+0x14)#define PTA_ICONFB2 (PTA_BASE_ADDR+0x18)#define PTA_DR (PTA_BASE_ADDR+0x1C)#define PTA_GIUS (PTA_BASE_ADDR+0x20)#define PTA_SSR (PTA_BASE_ADDR+0x24)#define PTA_ICR1 (PTA_BASE_ADDR+0x28)#define PTA_ICR2 (PTA_BASE_ADDR+0x2C)#define PTA_IMR (PTA_BASE_ADDR+0x30)#define PTA_ISR (PTA_BASE_ADDR+0x34)#define PTA_GPR (PTA_BASE_ADDR+0x38)#define PTA_SWR (PTA_BASE_ADDR+0x3C)#define PTA_PUEN (PTA_BASE_ADDR+0x40)//// ;---------------------------------------;// ; GPIO - PTB ; // ; $0021_C100 to $0021_C1FF ; // ;---------------------------------------; #define PTB_BASE_ADDR 0xF021C100#define PTB_DDIR PTB_BASE_ADDR#define PTB_OCR1 (PTB_BASE_ADDR+0x04)#define PTB_OCR2 (PTB_BASE_ADDR+0x08)#define PTB_ICONFA1 (PTB_BASE_ADDR+0x0C)#define PTB_ICONFA2 (PTB_BASE_ADDR+0x10)#define PTB_ICONFB1 (PTB_BASE_ADDR+0x14)#define PTB_ICONFB2 (PTB_BASE_ADDR+0x18)#define PTB_DR (PTB_BASE_ADDR+0x1C)#define PTB_GIUS (PTB_BASE_ADDR+0x20)#define PTB_SSR (PTB_BASE_ADDR+0x24)#define PTB_ICR1 (PTB_BASE_ADDR+0x28)#define PTB_ICR2 (PTB_BASE_ADDR+0x2C)#define PTB_IMR (PTB_BASE_ADDR+0x30)#define PTB_ISR (PTB_BASE_ADDR+0x34)#define PTB_GPR (PTB_BASE_ADDR+0x38)#define PTB_SWR (PTB_BASE_ADDR+0x3C)#define PTB_PUEN (PTB_BASE_ADDR+0x40)// ;---------------------------------------;// ; GPIO - PTC ;// ; $0021_C200 to $0021_C2FF ;// ;---------------------------------------;#define PTC_BASE_ADDR 0xF021C200#define PTC_DDIR PTC_BASE_ADDR#define PTC_OCR1 (PTC_BASE_ADDR+0x04)#define PTC_OCR2 (PTC_BASE_ADDR+0x08)#define PTC_ICONFA1 (PTC_BASE_ADDR+0x0C)#define PTC_ICONFA2 (PTC_BASE_ADDR+0x10)#define PTC_ICONFB1 (PTC_BASE_ADDR+0x14)#define PTC_ICONFB2 (PTC_BASE_ADDR+0x18)#define PTC_DR (PTC_BASE_ADDR+0x1C)#define PTC_GIUS (PTC_BASE_ADDR+0x20)#define PTC_SSR (PTC_BASE_ADDR+0x24)#define PTC_ICR1 (PTC_BASE_ADDR+0x28)#define PTC_ICR2 (PTC_BASE_ADDR+0x2C)#define PTC_IMR (PTC_BASE_ADDR+0x30)#define PTC_ISR (PTC_BASE_ADDR+0x34)#define PTC_GPR (PTC_BASE_ADDR+0x38)#define PTC_SWR (PTC_BASE_ADDR+0x3C)#define PTC_PUEN (PTC_BASE_ADDR+0x40)// ;---------------------------------------;// ; GPIO - PTD ;// ; $0021_C300 to $0021_C3FF ;// ;---------------------------------------;#define PTD_BASE_ADDR 0xF021C300#define PTD_DDIR PTD_BASE_ADDR#define PTD_OCR1 (PTD_BASE_ADDR+0x04)#define PTD_OCR2 (PTD_BASE_ADDR+0x08)#define PTD_ICONFA1 (PTD_BASE_ADDR+0x0C)#define PTD_ICONFA2 (PTD_BASE_ADDR+0x10)#define PTD_ICONFB1 (PTD_BASE_ADDR+0x14)#define PTD_ICONFB2 (PTD_BASE_ADDR+0x18)#define PTD_DR (PTD_BASE_ADDR+0x1C)#define PTD_GIUS (PTD_BASE_ADDR+0x20)#define PTD_SSR (PTD_BASE_ADDR+0x24)#define PTD_ICR1 (PTD_BASE_ADDR+0x28)#define PTD_ICR2 (PTD_BASE_ADDR+0x2C)#define PTD_IMR (PTD_BASE_ADDR+0x30)#define PTD_ISR (PTD_BASE_ADDR+0x34)#define PTD_GPR (PTD_BASE_ADDR+0x38)#define PTD_SWR (PTD_BASE_ADDR+0x3C)#define PTD_PUEN (PTD_BASE_ADDR+0x40)//// ;---------------------------------------;// ; LCDC ;// ; $0020_5000 to $0020_5FFF ;// ;---------------------------------------;#define LCDC_BASE_ADDR 0x00205000#define LCDC_PAL_ADDR 0x00205800#define LCDC_ssa LCDC_BASE_ADDR#define LCDC_xymax (LCDC_BASE_ADDR+0x04)#define LCDC_vpw (LCDC_BASE_ADDR+0x08)#define LCDC_hcc_xy (LCDC_BASE_ADDR+0x0C)#define LCDC_hcc_w (LCDC_BASE_ADDR+0x10)#define LCDC_chcc (LCDC_BASE_ADDR+0x14)#define LCDC_con (LCDC_BASE_ADDR+0x18)#define LCDC_hsyn (LCDC_BASE_ADDR+0x1C)#define LCDC_vsyn (LCDC_BASE_ADDR+0x20)#define LCDC_pan (LCDC_BASE_ADDR+0x24)#define LCDC_gpm (LCDC_BASE_ADDR+0x28)#define LCDC_pwm (LCDC_BASE_ADDR+0x2C)#define LCDC_dma (LCDC_BASE_ADDR+0x30)#define LCDC_self (LCDC_BASE_ADDR+0x34)#define LCDC_int (LCDC_BASE_ADDR+0x38)#define LCDC_status (LCDC_BASE_ADDR+0x40)#define LCDC_ram_0 LCDC_PAL_ADDR#define LCDC_ram_1 (LCDC_PAL_ADDR+0x04)#define LCDC_ram_2 (LCDC_PAL_ADDR+0x08)#define LCDC_ram_3 (LCDC_PAL_ADDR+0x0C)#define LCDC_ram_4 (LCDC_PAL_ADDR+0x10)#define LCDC_ram_5 (LCDC_PAL_ADDR+0x14)#define LCDC_ram_6 (LCDC_PAL_ADDR+0x18)#define LCDC_ram_7 (LCDC_PAL_ADDR+0x1C)#define LCDC_ram_8 (LCDC_PAL_ADDR+0x20)#define LCDC_ram_9 (LCDC_PAL_ADDR+0x24)#define LCDC_ram_a (LCDC_PAL_ADDR+0x28)#define LCDC_ram_b (LCDC_PAL_ADDR+0x2C)#define LCDC_ram_c (LCDC_PAL_ADDR+0x30)#define LCDC_ram_d (LCDC_PAL_ADDR+0x34)#define LCDC_ram_e (LCDC_PAL_ADDR+0x38)#define LCDC_ram_f (LCDC_PAL_ADDR+0x3c)//// ;---------------------------------------;// ; I2C ;// ; $0021_7000 to $0021_7FFF ;// ;---------------------------------------;//#define I2C_BASE_ADDR 0xF0217000#define I2C_IADR I2C_BASE_ADDR#define I2C_IFDR (I2C_BASE_ADDR+0x04)#define I2C_I2CR (I2C_BASE_ADDR+0x08)#define I2C_I2SR (I2C_BASE_ADDR+0x0C)#define I2C_I2DR (I2C_BASE_ADDR+0x10)//// ;---------------------------------------;// ; SSI ;// ; $0021_8000 to $0021_8FFF ;// ;---------------------------------------;#define SSI_BASE_ADDR 0x00218000#define SSI_STX SSI_BASE_ADDR#define SSI_SRX (SSI_BASE_ADDR+0x04)#define SSI_SCSR (SSI_BASE_ADDR+0x08)#define SSI_STCR (SSI_BASE_ADDR+0x0C)#define SSI_SRCR (SSI_BASE_ADDR+0x10)#define SSI_STCCR (SSI_BASE_ADDR+0x14)#define SSI_SRCCR (SSI_BASE_ADDR+0x18)#define SSI_STSR (SSI_BASE_ADDR+0x1C)#define SSI_SFCSR (SSI_BASE_ADDR+0x20)#define SSI_STR (SSI_BASE_ADDR+0x24)#define SSI_SOR (SSI_BASE_ADDR+0x28)//// ;---------------------------------------;// ; MMC all the address used for SDHC ;// ; $0021_4000 to $0021_4FFF ;// ;---------------------------------------;//#define MMC_BASE_ADDR 0x00214000#define MMC_STR_STP_CLK MMC_BASE_ADDR#define MMC_STATUS (MMC_BASE_ADDR+0x04)#define MMC_CLK_RATE (MMC_BASE_ADDR+0x08)#define MMC_CMD_DAT_CONT (MMC_BASE_ADDR+0x0C)#define MMC_RESPONSE_TO (MMC_BASE_ADDR+0x10)#define MMC_READ_TO (MMC_BASE_ADDR+0x14)#define MMC_BLK_LEN (MMC_BASE_ADDR+0x18)#define MMC_NOB (MMC_BASE_ADDR+0x1C)#define MMC_REV_NO (MMC_BASE_ADDR+0x20)#define MMC_INT_MASK (MMC_BASE_ADDR+0x24)#define MMC_CMD (MMC_BASE_ADDR+0x28)#define MMC_ARGH (MMC_BASE_ADDR+0x2C)#define MMC_ARGL (MMC_BASE_ADDR+0x30)#define MMC_RES_FIFO (MMC_BASE_ADDR+0x34)#define MMC_BUFFER_ACCESS (MMC_BASE_ADDR+0x38)#define MMC_BUF_PART_FULL (MMC_BASE_ADDR+0x3C)#define MMC_OTHERS_REGS_1 (MMC_BASE_ADDR+0x40)#define MMC_OTHERS_REGS_2 (MMC_BASE_ADDR+0x80)#define MMC_OTHERS_REGS_3 (MMC_BASE_ADDR+0x100)#define MMC_OTHERS_REGS_4 (MMC_BASE_ADDR+0x200)#define MMC_OTHERS_REGS_5 (MMC_BASE_ADDR+0x400)#define MMC_OTHERS_REGS_6 (MMC_BASE_ADDR+0x800)//// ;---------------------------------------;// ; MSHC ;// ; $0021_A000 to $0021_AFFF ;// ;---------------------------------------;#define MSHC_BASE_ADDR 0x0021A000#define MSHC_MSCMD MSHC_BASE_ADDR // ; Command Reg#define MSHC_MSCS (MSHC_BASE_ADDR+0x02) // ; Control/Status Reg#define MSHC_MSDATA (MSHC_BASE_ADDR+0x04) // ; Tx/Rx FIFO Reg#define MSHC_MSICS (MSHC_BASE_ADDR+0x06) // ; Interrupt Control/Status Reg#define MSHC_MSPPCD (MSHC_BASE_ADDR+0x08) // ; Parallel Port Control/Data Reg#define MSHC_MSC2 (MSHC_BASE_ADDR+0x0A) // ; Control2 Reg#define MSHC_MSACMD (MSHC_BASE_ADDR+0x0C) // ; Auto Command Reg#define MSHC_MSFAECS (MSHC_BASE_ADDR+0x0E) // ; FIFO Acc Err Ctrl/Status Reg#define MSHC_MSCLKD (MSHC_BASE_ADDR+0x10) // ; Serial Clock Div Control Reg#define MSHC_MSDRQC (MSHC_BASE_ADDR+0x12) // ; DMA Request Control Reg//// ;---------------------------------------;// ; PORTHOLE ;// ;---------------------------------------;#define EVENT_PORTHOLE 0x12301000 // ; User Event Porthole#define EVENT_PH 0x12301000#define EVENT 0x12301000#define PASS_PORTHOLE 0x12301004#define PASS_PH 0x12301004#define FAIL_PORTHOLE 0x12301008#define FAIL_PH 0x12301008#define STOP_PORTHOLE 0x1230100C#define STOP_PH 0x1230100C#define FINISH_PORTHOLE 0x12301010#define FINISH_PH 0x12301010//#define EXP_DATA_PH 0x12301014#define CODE_DATA_PH 0x12301018#define ADDR_DATA_PH 0x1230101C#define ACT_DATA_PH 0x12301020//#define EVENT_VALUE 0x0000beef // ; Code execution complete trigger#define USER_EVENT0_DATA 0xbadbeef0#define USER_EVENT1_DATA 0xbadbeef1#define USER_EVENT2_DATA 0xbadbeef2#define USER_EVENT3_DATA 0xbadbeef3#define USER_EVENT4_DATA 0xbadbeef4#define USER_EVENT5_DATA 0xbadbeef5#define USER_EVENT6_DATA 0xbadbeef6#define USER_EVENT7_DATA 0xbadbeef7#define USER_EVENT8_DATA 0xbadbeef8#define USER_EVENT9_DATA 0xbadbeef9#define USER_EVENT10_DATA 0xbadbeefa#define USER_EVENT11_DATA 0xbadbeefb#define USER_EVENT12_DATA 0xbadbeefc#define USER_EVENT13_DATA 0xbadbeefd#define USER_EVENT14_DATA 0xbadbeefe#define USER_EVENT15_DATA 0xbadbeeff#define MCU_JNT_HALT 0xdeaddead//// ;---------------------------------------;// ; PWM ;// ; $0020_8000 to $0020_8FFF ;// ;---------------------------------------;#define PWM1_BASE_ADDR 0x00208000#define PWMC1 PWM1_BASE_ADDR#define PWMS1 (PWM1_BASE_ADDR+0x04)#define PWMP1 (PWM1_BASE_ADDR+0x08)#define PWMCNT1 (PWM1_BASE_ADDR+0x0C)#define PWMTST1 (PWM1_BASE_ADDR+0x10)// ;---------------------------------------;// ; RAM ;// ; $0030_0100 to $0031_FFFF ;// ; $0030_0000 to $0030_00FF for PORTHOLE ;// ;---------------------------------------;#define RAM1_BASE_ADDR 0x00300100#define RAM1_END_ADDR (RAM1_BASE_ADDR+0x0FF00)#define RAM2_BASE_ADDR 0x00310000#define RAM2_END_ADDR (RAM2_BASE_ADDR+0x10000)#define TOP_OF_STACK 0x00320000//// ;---------------------------------------;// ; RTC ;// ; $0020_4000 to $0020_4FFF ;// ;---------------------------------------;#define RTC_BASE_ADDR 0x00204000#define RTC_HOURMIN RTC_BASE_ADDR⌨️ 快捷键说明
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