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!if $(A_S_IRQ_FIXED)
$(A_S_PIC_IRQ_TABLE)
!endif
! if "$(A_PCI_SLOT1)" != ""
// Slot 1
Package(){0x$(A_PCI_SLOT1)ffff, 0, LNKA, 0},
Package(){0x$(A_PCI_SLOT1)ffff, 1, LNKB, 0},
Package(){0x$(A_PCI_SLOT1)ffff, 2, LNKC, 0},
Package(){0x$(A_PCI_SLOT1)ffff, 3, LNKD, 0},
! endif
! if "$(A_PCI_SLOT2)" != ""
// Slot 2
Package(){0x$(A_PCI_SLOT2)ffff, 0, LNKB, 0},
Package(){0x$(A_PCI_SLOT2)ffff, 1, LNKC, 0},
Package(){0x$(A_PCI_SLOT2)ffff, 2, LNKD, 0},
Package(){0x$(A_PCI_SLOT2)ffff, 3, LNKA, 0},
! endif
! if "$(A_PCI_SLOT3)" != ""
// Slot 3
Package(){0x$(A_PCI_SLOT3)ffff, 0, LNKC, 0},
Package(){0x$(A_PCI_SLOT3)ffff, 1, LNKD, 0},
Package(){0x$(A_PCI_SLOT3)ffff, 2, LNKA, 0},
Package(){0x$(A_PCI_SLOT3)ffff, 3, LNKB, 0},
! endif
! if "$(A_PCI_SLOT4)" != ""
// Slot 4
Package(){0x$(A_PCI_SLOT4)ffff, 0, LNKD, 0},
Package(){0x$(A_PCI_SLOT4)ffff, 1, LNKA, 0},
Package(){0x$(A_PCI_SLOT4)ffff, 2, LNKB, 0},
Package(){0x$(A_PCI_SLOT4)ffff, 3, LNKC, 0},
! endif
! if "$(A_PCI_SLOT5)" != ""
// Slot 5
Package(){0x$(A_PCI_SLOT5)ffff, 0, LNKA, 0},
Package(){0x$(A_PCI_SLOT5)ffff, 1, LNKB, 0},
Package(){0x$(A_PCI_SLOT5)ffff, 2, LNKC, 0},
Package(){0x$(A_PCI_SLOT5)ffff, 3, LNKD, 0},
! endif
! if "$(A_PCI_SLOT6)" != ""
// Slot 6
Package(){0x$(A_PCI_SLOT6)ffff, 0, LNKA, 0},
Package(){0x$(A_PCI_SLOT6)ffff, 1, LNKB, 0},
Package(){0x$(A_PCI_SLOT6)ffff, 2, LNKC, 0},
Package(){0x$(A_PCI_SLOT6)ffff, 3, LNKD, 0},
! endif
! if "$(A_PCI_DEV1_IRQA)" != ""
// Device 1, IRQA
Package(){0x$(A_PCI_DEV1_IRQA:.=), LNKA, 0},
! endif
! if "$(A_PCI_DEV1_IRQB)" != ""
// Device 1, IRQB
Package(){0x$(A_PCI_DEV1_IRQB:.=), LNKB, 0},
! endif
! if "$(A_PCI_DEV1_IRQC)" != ""
// Device 1, IRQC
Package(){0x$(A_PCI_DEV1_IRQC:.=), LNKC, 0},
! endif
! if "$(A_PCI_DEV1_IRQD)" != ""
// Device 1, IRQD
Package(){0x$(A_PCI_DEV1_IRQD:.=), LNKD, 0},
! endif
! if "$(A_PCI_DEV2_IRQA)" != ""
// Device 2, IRQA
Package(){0x$(A_PCI_DEV2_IRQA:.=), LNKA, 0},
! endif
! if "$(A_PCI_DEV2_IRQB)" != ""
// Device 2, IRQB
Package(){0x$(A_PCI_DEV2_IRQB:.=), LNKB, 0},
! endif
! if "$(A_PCI_DEV2_IRQC)" != ""
// Device 2, IRQC
Package(){0x$(A_PCI_DEV2_IRQC:.=), LNKC, 0},
! endif
! if "$(A_PCI_DEV2_IRQD)" != ""
// Device 2, IRQD
Package(){0x$(A_PCI_DEV2_IRQD:.=), LNKD, 0},
! endif
! if "$(A_PCI_DEV3_IRQA)" != ""
// Device 3, IRQA
Package(){0x$(A_PCI_DEV3_IRQA:.=), LNKA, 0},
! endif
! if "$(A_PCI_DEV3_IRQB)" != ""
// Device 3, IRQB
Package(){0x$(A_PCI_DEV3_IRQB:.=), LNKB, 0},
! endif
! if "$(A_PCI_DEV3_IRQC)" != ""
// Device 3, IRQC
Package(){0x$(A_PCI_DEV3_IRQC:.=), LNKC, 0},
! endif
! if "$(A_PCI_DEV3_IRQD)" != ""
// Device 3, IRQD
Package(){0x$(A_PCI_DEV3_IRQD:.=), LNKD, 0},
! endif
! if "$(A_PCI_DEV4_IRQA)" != ""
// Device 4, IRQA
Package(){0x$(A_PCI_DEV4_IRQA:.=), LNKA, 0},
! endif
! if "$(A_PCI_DEV4_IRQB)" != ""
// Device 4, IRQB
Package(){0x$(A_PCI_DEV4_IRQB:.=), LNKB, 0},
! endif
! if "$(A_PCI_DEV4_IRQC)" != ""
// Device 4, IRQC
Package(){0x$(A_PCI_DEV4_IRQC:.=), LNKC, 0},
! endif
! if "$(A_PCI_DEV4_IRQD)" != ""
// Device 4, IRQD
Package(){0x$(A_PCI_DEV4_IRQD:.=), LNKD, 0},
! endif
//-----------------------------------------------------------------------
} )
! else
Include("$(ACPI_ASL_PATH)CUST_irq.oem")
! endif
//-----------------------------------------------------------------------
// PCI-ISA (SOUTH) BRIDGE
//-----------------------------------------------------------------------
Device(SBRG) {
Name(_ADR, 0x$(A_S_DEV_Nbr)0000)
! if !$(A_THERMAL) && ("$(A_FAN_PATH)" != "")
// Keep the FAN On whenever the parent Device On
Name(_PR0, Package(){GFAN})
! endif
// PCI interrupt routing devices
Name(\_SB.IPRS, // List of possible IRQs
// to be returned by _PRS for LINKx devices
ResourceTemplate()
{
StartDependentFnNoPri()
{
IRQ(Level, ActiveLow, Shared ) {$(A_PCI_IRQ_LIST)} // 3,4,5,6,7,9,10,11,12,14,15
}
EndDependentFn()
})
Include("$(ACPI_ASL_PATH)irq-pci.asl")
//-----------------------------------------------------------------------
// Miscellaneous I/O Ports
//-----------------------------------------------------------------------
// This table should contain any I/O port that is not used by a specific
// device but does not return FFh when read. Some examples of I/O ports
// that should be reserved here are:
// The I/O peripheral chip's index/data ports
// Any I/O port in the range 00 - FF that is not used by any other dev node
// The IRQ edge/level control ports (4D0/4D1)
//-----------------------------------------------------------------------
// For example:
// ASL macro "FixedIO"
// FixedIO( WordConst, // _BAS, Address base
// ByteConst // _LEN, Range length
// )
// if SuperIO module Index/Data port address allocated in
// 0x3f0 / 0x3f1 we need to update "FixedIO" macro with
// "Address base" = 0x3f0 and "Range length" = 0x02
// FixedIO( 0x3f0, 0x02)
// ^^^ ^^ fields only to edit
//-----------------------------------------------------------------------
Device(SYSR) {
Name(_HID, EISAID("PNP0C02"))
Method(_STA, 0)
{
If(OSFL) // If running under Win98?
{
Return(0x0f) // Device present
}
Return(0x0) // Not present if NT 5.0
}
Name(IORG,
ResourceTemplate()
{
FixedIO(0x10, 0x10)
FixedIO(0x22, 0x1e)
FixedIO(0x44, 0x1c)
FixedIO(0x62, 0x02)
FixedIO(0x65, 0x0b)
FixedIO(0x72, 0x0E)
FixedIO(0x80, 0x01)
FixedIO(0x84, 0x03)
FixedIO(0x88, 0x01)
FixedIO(0x8C, 0x03)
FixedIO(0x90, 0x10)
FixedIO(0xa2, 0x1e)
FixedIO(0xe0, 0x10)
// LM78/79 or W8378x Hardware Monitor ICs
FixedIO(0x290, 0x8)
// Decoded but not used by FDC
// IO(Decode16, 0x3f3, 0x3f3, 0, 0x1)
// Abel Wu
!if $(A_S_ALI1543)
// Reserve 40B for Extended DMA1 Mode port
IO(Decode16, 0x40b, 0x40b, 0, 0x1)
!endif
!if $(A_S_SIS5595) || $(A_S_ALI1543)
// Reserve 480 - 48F for Extended DMA ports
IO(Decode16, 0x480, 0x480, 0, 0x10)
!endif
// Reserve 4D0 and 4D1 for IRQ edge/level control port
IO(Decode16, 0x4d0, 0x4d0, 0, 0x2)
!if $(A_S_ALI1543)
// Reserve 4D6 for Extended DMA2 Mode port
IO(Decode16, 0x4d6, 0x4d6, 0, 0x1)
!endif
!if $(A_PMU_ALL)
// PM base address allocation
IO(Decode16, 0, 0, 0, 0x0, IO1)
// SMBus base address allocation
IO(Decode16, 0, 0, 0, 0x0, IO2)
!endif
!if "$(IO_INDEX_PORT)" != ""
// Index\Data for Super I/O
IO(Decode16, 0x$(IO_INDEX_PORT:h=), 0x$(IO_INDEX_PORT:h=), 0, 0x2)
!endif
// Abel Wu
!if $(A_S_VIA82586)
! if $(SUPER_SOUTH_BR)
// VIA 82C686 Hardware Monitor I/O Ports
IO(Decode16, 0x$(HW_BASE_HIGH:h=)00, 0x$(HW_BASE_HIGH:h=)00, 0, 0x80)
! endif
!endif
!if $(A_S_SIS5595)
// Reserve Unknow memory FFEF0000-FFEFFFFF
Memory32(ReadOnly, 0xffef0000, 0xffef0000, 0, 0x10000)
!endif
} // End of ResourceTemplate
) // end of IORG
Method(_CRS, 0)
{
!if $(A_PMU_ALL)
CreateWordField(IORG, \_SB.PCI0.SBRG.SYSR.IO1._MIN, PM00) // PM Base
CreateWordField(IORG, \_SB.PCI0.SBRG.SYSR.IO1._MAX, PM01)
CreateByteField(IORG, \_SB.PCI0.SBRG.SYSR.IO1._LEN, PMLN) // PM Length
CreateWordField(IORG, \_SB.PCI0.SBRG.SYSR.IO2._MIN, SM00) // SMB Base
CreateWordField(IORG, \_SB.PCI0.SBRG.SYSR.IO2._MAX, SM01)
CreateByteField(IORG, \_SB.PCI0.SBRG.SYSR.IO2._LEN, SMLN) // SMB length
Store(\_SB.PCI0.PMU.PMBS(), PM00)
Store(PM00, PM01)
If(PM00) // If Base <> 0 : set length to 40
{ // Otherwise to 0
// Abel Wu
!if $(A_S_VIA82586)
Store(0x80, PMLN)
!else
Store(0x40, PMLN)
!endif
}
Store(\_SB.PCI0.PMU.SMBS(), SM00)
Store(SM00, SM01)
If(SM00) // If Base <> 0 : set length to 10
{ // Otherwise to 0
// Abel Wu
!if $(A_S_ALI1543)
Store(0x20, SMLN)
!else
Store(0x10, SMLN)
!endif
}
!endif
Return(IORG)
}
} // End System Resources SYSR
/////////////////////////////////////////////////////////////////////////
// System board extension for ACPI BIOS
// Place that device under \_SB scope, As per Msft the MEM
// Resources should not be declared neither in PCI0 nor in PCI-ISA Bus
/////////////////////////////////////////////////////////////////////////
Device(\_SB.MEM) { // Memory
Name(_HID, EISAID("PNP0C01")) // Hardware Device ID
Method (_STA, 0)
{
If(\_SB.PCI0.OSFL) // If running under Win98?
{
Return(0x0f) // Device present
}
Return(0x0) // Not present
}
Name(MEM1,
ResourceTemplate()
{
// Base Address 0 - 0x9FFFF , 640k DOS memory
Memory32Fixed(ReadWrite, 0x0000, 0xA0000 )//Writeable
// Base Address F000 - 1M , 64k BIOS
Memory32Fixed(ReadOnly, 0xF0000, 0x10000 )//Non-writeable
// Base Address 1M - Top of system present memory
Memory32Fixed(ReadWrite, 0x100000, 0x1FF00000, TOPM)//Writeable
!if $(NCPU) > 1
// Local & IO APIC memory reservation. Make sure addresses are compliant to ACPI APIC table
! ifdef MPS_SUPPORT
! if $(MPS_SUPPORT)
Memory32Fixed(ReadOnly, 0xFEC00000, 0x1000 )// APIC Non-Writeable
! endif
! endif
Memory32Fixed(ReadOnly, 0xFEE00000, 0x1000 )// APIC Non-Writeable
!endif
Memory32Fixed(ReadOnly, 0xFFFF0000, 0x10000)//Non-Writeable, 64K ROM image
})
Method (_CRS, 0)
{
// Top of memory
// MDET Control Method returns available system memory
CreateDwordField(MEM1, \_SB.MEM.TOPM._LEN, TOP1)
// MDET defined in \_SB.PCI0 scope
Subtract(\_SB.PCI0.MDET(), 0x100000, TOP1)
Return(MEM1)
} // end of _CRS
} // End Memory
//-----------------------------------------------------------------------
// ONBOARD I/O Standard peripherals
// DMA, Keyboard, Timer, Speaker, CMOS...
//-----------------------------------------------------------------------
Include("$(ACPI_ASL_PATH)sysstand.asl")
!if $(A_KEY_WAKE_UP)
// Resume by key pressed
Name(PS2K._PRW, Package(){0x$(A_KEY_GPE), 0x$(A_KEY_WAK_SYST)})
/* An example of resume code can be used on particular designs if event handler is needed
Method(PS2K._PSW, 1)
{
If(Arg0){ } // Enable resume by Keyboard
Else
{ } // Disable resume
}
Scope(\_GPE)
{
Method(_L$(A_KEY_GPE))
{
// OEM ASL code
Notify(\_SB.PCI0.SBRG.PS2K, 0x2) // Wake up event
}
}
*/
!endif
!if $(A_MOUSE_WAKE_UP)
// Resume by key pressed
Name(PS2M._PRW, Package(){0x$(A_MOUSE_GPE), 0x$(A_MOUSE_WAK_SYST)})
!endif
!if $(A_POS_DECODE)
// Device(EIO) {
// Name(_HID, EISAID("PNP0A06"))
// Methods for routing/release IO/DMA resources on EIO bus
Include("$(ACPI_ASL_PATH)eioroute.asl")
!else
// Route and Release I/O, DMA resources to EIO Bus
// Dummy methods
Method(RRIO, 4) { NoOp }
Method(RGNR, 4) { NoOp }
Method(rDMA, 3) { NoOp }
!endif
!if "$(A_OEMIO_PATH_SUPERIO)" != ""
Name(SPIO, 0x$(IO_INDEX_PORT:h=)) // Super I/O Index/Data base address
//-----------------------------------------------------------------------
// Super IO devices (FDC, UART1,2, LPT, ECP, IR)
//-----------------------------------------------------------------------
Include("$(ACPI_ASL_PATH)superio.asl")
!if $(A_SUPER_IO_PM) || $(A_RI_WAKE_UP_UART1)
Name(UAR1._PR0, Package(){URP1}) // Reference to PowerResources
!endif
!if $(A_SUPER_IO_PM) || $(A_RI_WAKE_UP_UART2)
Name(UAR2._PR0, Package(){URP2}) // Reference to PowerResources
!endif
! if $(A_SUPER_IO_PM)
Name(FDC0._PR0, Package(){FDDP}) // Reference to PowerResources
Name(ECP._PR0, Package(){LPTP}) // Reference to PowerResources
Name(LPT._PR0, Package(){LPTP}) // Reference to PowerResources
! endif
!if $(A_RI_WAKE_UP_UART1)
// Resume by modem Ring
Name(UAR1._PRW, Package(){0x$(A_RI_GPE), 0x$(A_RI_WAK_SYST)})
!endif
!if $(A_RI_WAKE_UP_UART2)
// Resume by modem Ring
Name(UAR2._PRW, Package(){0x$(A_RI_GPE), 0x$(A_RI_WAK_SYST)})
!endif
!endif
!if "$(A_OEMIO_PATH_AUDIO)" != ""
Include("$(ACPI_ASL_PATH)audio.asl")
!endif
!if $(A_OEM_ISA_DEV)
// OEM ISA device
Include("$(ACPI_ASL_PATH)cust_isa.oem")
!endif
!if $(A_POS_DECODE)
// } // end of EIO bus
!endif
} // End of SBRG
!if $(A_PMU_ALL)
//-----------------------------------------------------------------------
// PCI Power Management Unit (PMU)
//-----------------------------------------------------------------------
Device(PMU) {
Name(_ADR, 0x$(A_PMU_DEV_FUN_Adr))
// Contains the PMBS & SMBS control methods to return the PM & SMBus I/O base address
!ifdef PM_BASE_HIGH
Method(PMBS,0) { // Return Power Management I/O base address
Or(ShiftLeft(0x$(PM_BASE_HIGH:h=),8), 0x$(PM_BASE_LOW:h=), Local0)
Return(Local0)
}
Method(SMBS,0) { // Return SMBus I/O base address
Or(ShiftLeft(0x$(SMB_BASE_HIGH:h=),8), 0x$(SMB_BASE_LOW:h=), Local0)
Return(Local0)
}
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