gpminit.inc

AMI 主板的BIOS源码。

Subttl.	Include file for GREEN PC support INIT code...GPMINIT.INC

;-----------------------------------------------;
;  FOLLOWING ROUTINES USED FROM OTHER MODULES	;
;-----------------------------------------------;

	public	init_smram			;
	public	init_smram_early_post		;

;-----------------------------------------------;
;*****************************************************************;
;*****************************************************************;
;**								**;
;**	(C)Copyright 1985-1996, American Megatrends Inc.	**;
;**								**;
;**			All Rights Reserved.			**;
;**								**;
;**		6145-F, Northbelt Parkway, Norcross,		**;
;**								**;
;**		Georgia - 30071, USA. Phone-(770)-246-8600.	**;
;**								**;
;*****************************************************************;
;*****************************************************************;
;---------------------------------------------------------------;
;	    POST TIME CORE BIOS SMI/IRQ HANDLER CODE		;
;	    POST TIME CORE BIOS SMI/IRQ HANDLER CODE		;
;	    POST TIME CORE BIOS SMI/IRQ HANDLER CODE		;
;	    POST TIME CORE BIOS SMI/IRQ HANDLER CODE		;
;---------------------------------------------------------------;
;			INIT_SMRAM_EARLY_POST			;
;---------------------------------------------------------------;
;	Input :	(CS) SMI code source segment			;
;		STACK PRESENT					;
;	Output: (CY) 00 successful				;
;		(CY) 01 error					;
;	Register destroyed : NONE				;
; NOTE :							;
;  *  Control comes here to initialize smram with the smi handler
;     during early post for USB etc.				;
;  *  In this routine (BL) is used to keep different info at	;
;     different point of time....				;
;	(BL) bit 0 0 means 64KB or greater SMRAM		;
;		   1 means 32KB SMRAM				;
;	     bit 1 0 means init_smram_early_post not done	;
;		   1 means init_smram_early_post done		;
;	     bit 1 0 means smbase relocation not required	;
;		   1 means smbase relocation is required	;
;	     bit 3  bit 2					;
;	       0      0   ... INTEL type SMI			;
;	       0      1   ... CYRIX type SMI			;
;	       1      0   ... AMD type SMI			;
;	       1      1   ... reserved				;
;	     bit 4 set for dual/multiple CPU present		;
;	     bit 4 clear for single CPU				;
;	     bit 5 set for IRQ based power management		;
;	     bit 5 clear for SMI based power management		;
;	     bit 6 set for SMI capable CPU			;
;	     bit 6 clear for non-SMI CPU			;
;	     bit 7 0 means smi init called during late post	;
;		   1 means smi init called during early post	;
;	     bit 7 0 means smi post was successful		;
;		   1 means smi post was unsuccessful		;
;  *  This routine is called from the main bios	hook in early	;
;     post to make USB kb/mouse device available.		;
;  *  It is assumed all SMI sources are disabled at this point	;
;---------------------------------------------------------------;

init_smram_early_post	proc	near

	push	ax				;
	mov	al,smi_init_early_post		; bit 7 1 to identify early post SMRAM initialization for USB etc.
	call	init_smram_local		;
	jc	short init_smram_early_post_00	; error...

	push	ds				;
	push	bios_data_seg			;
	pop	ds				; (ds) = bios standard data segment (40H)
	or	bda_apm_state,early_post_init_smram_done; set bit 1
	pop	ds				;

init_smram_early_post_00:
	pop	ax				;
	ret

init_smram_early_post	endp

;---------------------------------------------------------------;
;			     INIT_SMRAM				;
;---------------------------------------------------------------;
;	Input :	(CS) SMI code source segment			;
;		STACK PRESENT					;
;	Output: (CY) 00 successful				;
;		(CY) 01 error					;
;	Register destroyed : NONE				;
; NOTE :							;
;  *  Control comes here to initialize smram with the smi handler
;  *  In this routine (BL) is used to keep different info at	;
;     different point of time....				;
;	(BL) bit 0 0 means 64KB or greater SMRAM		;
;		   1 means 32KB SMRAM				;
;	     bit 1 0 means init_smram_early_post not done	;
;		   1 means init_smram_early_post done		;
;	     bit 1 0 means smbase relocation not required	;
;		   1 means smbase relocation is required	;
;	     bit 3  bit 2					;
;	       0      0   ... INTEL type SMI			;
;	       0      1   ... CYRIX type SMI			;
;	       1      0   ... AMD type SMI			;
;	       1      1   ... reserved				;
;	     bit 4 set for dual/multiple CPU present		;
;	     bit 4 clear for single CPU				;
;	     bit 5 set for IRQ based power management		;
;	     bit 5 clear for SMI based power management		;
;	     bit 6 set for SMI capable CPU			;
;	     bit 6 clear for non-SMI CPU			;
;	     bit 7 0 means smi init called during late post	;
;		   1 means smi init called during early post	;
;	     bit 7 0 means smi post was successful		;
;		   1 means smi post was unsuccessful		;
;  *  This routine is called from the main bios	hook 'SPECIAL_	;
;     CONFIG_DISPLAY' at check point 0AAh			;
;  *  It is assumed all SMI sources are disabled at this point	;
;---------------------------------------------------------------;

init_smram	proc	near

	push	ax				;
	mov	al,00000000b			; bit 7 0 to identify normal SMRAM initialization
	call	init_smram_local		;
	pop	ax				;
	ret

init_smram	endp

;---------------------------------------------------------------;
;			INIT_SMRAM_LOCAL			;
;---------------------------------------------------------------;
;	Input :	(CS) SMI code source segment			;
;		(AL) bit 0 set...called during early post	;
;		     bit 0 clear...called during late post	;
;		STACK PRESENT					;
;	Output: (CY) 00 successful				;
;		(CY) 01 error					;
;	Register destroyed : NONE				;
; NOTE :							;
;  *  Control comes here to initialize smram with the smi handler
;  *  In this routine (BL) is used to keep different info at	;
;     different point of time....				;
;	(BL) bit 0 0 means 64KB or greater SMRAM		;
;		   1 means 32KB SMRAM				;
;	     bit 1 0 means init_smram_early_post not done	;
;		   1 means init_smram_early_post done		;
;	     bit 1 0 means smbase relocation not required	;
;		   1 means smbase relocation is required	;
;	     bit 3  bit 2					;
;	       0      0   ... INTEL type SMI			;
;	       0      1   ... CYRIX type SMI			;
;	       1      0   ... AMD type SMI			;
;	       1      1   ... reserved				;
;	     bit 4 set for dual/multiple CPU present		;
;	     bit 4 clear for single CPU				;
;	     bit 5 set for IRQ based power management		;
;	     bit 5 clear for SMI based power management		;
;	     bit 6 set for SMI capable CPU			;
;	     bit 6 clear for non-SMI CPU			;
;	     bit 7 0 means smi init called during late post	;
;		   1 means smi init called during early post	;
;	     bit 7 0 means smi post was successful		;
;		   1 means smi post was unsuccessful		;
;  *  It is assumed all SMI sources are disabled at this point	;
;---------------------------------------------------------------;

init_smram_local	proc	near

	pushad					;
	push	ds				;
	push	es				;
	push	ax				; save early/late post info in bit 7 of (AL)

	cld					; clear direction flag
	call	get_cpu_id_local		; returns (dx:ax) pointer to ASCIIZ cpu name string
						; (cl) cpu number, (bx) function field
	push	bx				; save function field
	call	get_vendor_name_local		; (bl) = cpu vendor number
	mov	ch,bl				; (ch) = cpu vendor number, (cl) = cpu number
	pop	bx				; (bl) bit 7 SMI support info
						; (bh) bit 6 & 5 has SMI type support info for 10/10/94 and above CORE BIOS
	pop	ax				; restore early/late post info in bit 7 of (AL)
	cmp	ch,0ffh				; unknown CPU vendor ?
	jz	short init_smram_00		; exit...can not support power management

	call	set_smi_type			; set/reset bit 2 & 3 of (bh) for proper SMI type (INTEL/CYRIX/AMD)
						; set/reset bit 6 of (bh) for SMI/non-SMI CPU
						; all other bits of (bh) will be reset to 0
						; DOES NOT DESTROY (AL)

	or	bh,al				; set early/late post info in bit 7
	call	get_dual_cpu_info		; set/reset bit 4 of (bh) for dual cpu present/absent
						; setup bits 3 thru 0 of (bl) according to # of secondary CPU

	call	select_pm_method		; CHIPSET HOOK HOOK HOOK...returns (al) = 0/1/2/3
	call	save_pm_method			; save power management method in global data area
;if (MKF_SOFT_OFF)
	jmp	short init_smram_50		; yes...
;else
;	cmp	al,1				; use SMI based power management ?
;	jz	short init_smram_50		; yes...
;endif
;-----------------------------------------------;

init_smram_40:
	cmp	al,3				; IRQ based power management ?
	jz	short init_irq_pm		; yes...
	cmp	al,2				; hardware automatic power management ?
	jnz	short init_smram_00		; no...disable power management

;-----------------------------------------------;

init_hw_auto_pm:
	call	setup_hw_auto_pm		; CHIPSET HOOK HOOK HOOK...setup for automatic hardawre power management
	jmp	init_smram_08			;

;-----------------------------------------------;

init_irq_pm:

IF	IRQ_HANDLING_SUPPORT
	or	bh,irq_power_management		; set for IRQ based power management
	shl	ah,4				; (ah) = get IRQ level in high nibble
	and	bl,00001111b			; clear higher nibble
	or	bl,ah				; (bl) higher nibble contains IRQ level selected
	jmp	short init_smram_50		; go to common path as SMI based power management
ELSE
	jmp	short init_smram_00		; currently IRQ based power management not supported
ENDIF

;-----------------------------------------------;

init_smram_17:
	call	clear_default_smram		;
init_smram_18:
	or	bl,smi_post_failure		; (bl) bit 7 set for smi post unsuccessful
	call	close_smram			; CHIPSET HOOK HOOK HOOK...close SMRAM space
init_smram_00:
	xor	al,al				; disable power management
	call	save_pm_method			; save power management method in global data area
	stc					; (cy) = 01 for premature exit
init_smram_19:
	jmp	init_smram_09			;

;-----------------------------------------------;

init_smram_50:
	xchg	bl,bh				; (bl) used as temp info byte
						; (bh) bits 3-0 .. # of secondary CPU present
						; (bh) bits 7-4 .. IRQ level selected for IRQ based power management

	call	get_mapped_smi_seg_and_size	; CHIPSET HOOK HOOK HOOK...returns mapped smram segment info for different CPU and the size of SMRAM
	call	determine_smram_size		; set/reset bit 0 of (bl)
	jc	short init_smram_00		; exit...can not support 32KB SMRAM for IBM/AMD non-PLUS CPUs
	call	open_smram			; CHIPSET HOOK HOOK HOOK...open the SMRAM space for initialisation
	jc	short init_smram_18		; error in opening SMRAM space...exit
						; returns (edi) = absolute address where SMI handler should be copied to

	test	bl,smram_size_32kb		; is it 32KB SMRAM ?
	jz	short init_smram_02		; no...64KB or greater SMRAM
	sub	edi,8000h			; align 32KB SMRAM in 64KB form
init_smram_02:
	shr	edi,4				; (di) = segment where SMI code will be copied to
						; we will use [di:8000h] to [di:ffffh], so both
						; 32KB and 64KB SMRAM should work

	push	bios_data_seg			;
	pop	ds				; (ds) = bios standard data segment (40H)
	mov	al,bda_apm_state		; (al) = current bda_apm_state
	and	bda_apm_state,not early_post_init_smram_done; clear bit 1
	and	al,early_post_init_smram_done	;
	or	bl,al				; set/reset bit 1 for early_post_init_smram done

	mov	ds,di				; set (ds) to SMRAM segment
	mov	es,di				; set (es) to SMRAM segment

	test	bl,smi_init_early_post		; SMI initialization code is being called during early post ?
	jnz	short init_smram_61		; yes...
	test	bl,early_post_init_smram_done	; early_post_init_smram done ?
	jnz	short init_smram_62		; yes...
init_smram_61:

	call	clear_smram			; clear SMRAM area
	call	copy_compare_smram		; copy SMI code into SMRAM and compare
	jc	short init_smram_18		; error in SMI code compare

	call	init_smi_cpu_data		; initialise SMI data area related to CPU
	call	setup_cpu_jmp_code		; setup CPU JMP vectors

	test	bl,smi_init_early_post		; SMI initialization code is being called during early post ?
	jnz	short init_smram_60		; yes...

init_smram_62:
	call	init_smi_data			; initialise SMI data area
	call	apm_post			; initialise APM data area
	call	init_pm_registers		; CHIPSET HOOK HOOK HOOK...initialise power management registers based on BCP/SETUP info
	test	bl,early_post_init_smram_done	; early_post_init_smram done ?
	jnz	short init_smram_64		; yes...
init_smram_60:
	call	handle_smbase_relocation	; set/reset bit 1 of (bl)
	jc	short init_smram_17		; error...
	call	setup_smi_handler_for_multiple_cpu; setup SMI handler for all secondary cpu
	jc	short init_smram_17		; error...EXIT
	push	bx				; save bit 7 of (BL) having SMI init at early/late post info
	and	bl,not smi_post_failure		; set SMI POST was successful
						; smi_init_early_post & smi_post_failure are sharing the same bit
	call	close_smram			; CHIPSET HOOK HOOK HOOK...close SMRAM space
	pop	bx				; restore bit 7 of (BL) having SMI init at early/late post info
	call	relocate_smbase_for_multiple_cpu; relocate SMBASE for all secondary cpu
	jc	short init_smram_00		; error...EXIT
	call	global_smi_enable		; CHIPSET HOOK HOOK HOOK...set for SMI generation
	test	bl,smbase_reloc_reqd		; relocation needed ?
	jz	short init_smram_08		; no...
	call	generate_sw_smi_for_relocation	; CHIPSET HOOK HOOK HOOK...generate software SMI for relocation
	call	clear_default_smram		;
init_smram_08:
	clc					; (cy) = 00 for no error
init_smram_09: