📄 bup6.asm
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add eax,sizeof UpdateHeaderStruc; EAX = 32bit address of actual update data
mov ecx,00000079h ; ECX = 00000079h
xor edx,edx ; EDX = 00000000h
wrmsr ; trigger BIOS update in processor
call get_processor_update_revision; EDX = processor update revision
cmp ebx,edx ; update revision must match
jz bl01_09 ; processor accepts the update
; error, processor rejects the update
popad
mov ah,security_failure ; error code
jmp short bl01_10
bl01_08:
popad
mov ah,invalid_revision ; error code
bl01_10:
pop es
jmp bl01_00 ; exit
bl01_09:
; ES:DI = ptr to block where data will be updated
; DS:SI = ptr to source buffer
call get_sum_of_update_area
push eax
push es
bl01_43:
mov cx,block_length ; #of BYTES to move
bl01_40:
mov al,ds:[si]
mov es:[di],al
inc si
inc di
jnz bl01_41 ; not cross boundary..
mov es,bp ; next buffer (scratch pad2)
bl01_41:
loop bl01_40 ; next byte
; Update the checksum adjustment of microcode module
pop es
pop ebx ; EBX = sum of microcode module (in dwords) before updating
call get_sum_of_update_area
sub ebx,eax ; get difference in ebx
mov esi,cgroup:micro_code_start_addr
movzx eax,cgroup:word ptr update_blocks
shl eax,11 ; 2K unit
add esi,eax ; get to the end of the module
push esi
pop di
pop ax
mov esi,cgroup:micro_code_start_addr
shr esi,16
cmp ax,si ; cross the 64k boundary ?
jz bl01_45 ; no..
mov es,bp ; use scratch pad2
bl01_45:
or ebx,ebx ; need to adjust ?
jz bl01_46 ; no..
and di,0fffch ; dword align
add dword ptr es:[di+4],ebx ; add the adjustment
bl01_46:
popad
pop es
; update flash from scratch pad1:0000, 64K
; scratch pad2:0000, 64K
; CX = segment having 1st 64k of flash
; DX = segment having 2nd 64k of flash
pushad
mov es,cx ; ES = segment having 1st 64k of NVRAM storage
push es
push dx
call e000_read_rom_write_x ; enable ROM
call flash_write_enable ; enable flash write
call go_to_flat_mode_stack ; go to flat mode
pop dx
pop es
xor esi,esi ; ES:ESI = source buffer
mov edi,cgroup:micro_code_start_addr
and edi,0ffff0000h ; 0:EDI = 1st flash
; DS:EDI = ptr flash in flat mode..
xor cx,cx ; #of bytes to write
mov bx,cgroup:word ptr flash_found_table
cmp bx,0ffffh ; Flash found ?
stc
jz bl01_11 ; no flash part found
call cs:word ptr [bx+2] ; erase
jc bl01_11 ; error in erasing
call cs:word ptr [bx+4] ; program
jc bl01_11 ; error in programming
mov es,dx ; 2nd segment
xor esi,esi ; ES:ESI = source buffer
mov edi,cgroup:micro_code_start_addr
and edi,0ffff0000h
add edi,000010000h ; 0:EDI = 2nd flash
; DS:EDI = ptr flash in flat mode..
xor cx,cx ; 64K
cmp edi,0FFFF0000h ; 2nd is F000 sgement ?
jne bl01_20 ; no.. 64K can be written
mov cx,48*1024 ; CX = #of bytes in F000 segment
bl01_20:
call cs:word ptr [bx+2] ; erase
jc bl01_11 ; error in erasing
call cs:word ptr [bx+4] ; program
bl01_11:
pushf ; save status of programming flash
call comeback_from_flat_mode_stack
call flash_write_disable ; disable write to flash
popf
popad
mov ah,success ; ok
jnc bl01_00
mov ah,write_failure ; error
bl01_00:
pop si
pop di
pop ds
pop es
ret
;-----------------------------------------------------------------------;
; Input:
; ES = scratch pad1:0
; BP = scratch pad2:0
; Output:
; EAX = sum of updateing area in dwords
;-----------------------------------------------------------------------;
get_sum_of_update_area:
push es
push di
push cx
mov di,word ptr cgroup:micro_code_start_addr ; di = offset in scratch pad1
xor eax,eax ; (eax) = dword checksum before updating
test di,03h ; dword boundary ?
jz sum_exit ; yes.. no need to update checksum
and di,0fffch ; dword alignment
mov cx,cgroup:word ptr update_blocks
shl cx,(11-2) ; in dwords
add cx,1+2 ; 1 dword = not in dword alignment, 2 dwords = checksum adjustment
sum_01:
add eax,es:[di]
add di,4 ; next dword
jnz sum_02
mov es,bp ; next buffer (scratch pad2)
sum_02:
loop sum_01
sum_exit:
pop cx
pop di
pop es
ret
;-----------------------------------------------------------------------;
; BIOS UPDATE CONTROL ;
; this function enables loading of binary updates into the processor. ;
; input : ;
; AX D042 ;
; BL 02 ;
; BH Task ;
; 1 Enable update loading during initialization time ;
; 2 Return the current state of update control without ;
; changing its status ;
; CX Scratch Pad1 (Real Mode Scratch segment 64K in length) ;
; DX Scratch Pad2 (Real Mode Scratch segment 64K in length) ;
; SI Scratch Pad3 (Real Mode Scratch segment 64K in length) ;
; SS:SP Stack (32K minimum) ;
; output: ;
; CF return status ;
; NC = success ;
; CY = error ;
; AH return code ;
; AL additional OEM information ;
; BL Enable/Disable indicator ;
; 0 = Disabled, 1 = Enabled ;
; note : ;
; 1. this function allows the caller to determine the current status of ;
; update loading without changing its status. ;
; 2. this function allows the caller to enable the update loading at ;
; initialization time. ;
; 3. this function does NOT allow the caller to disable loading of ;
; binary updates as this poses security risk. The system BIOS mantains ;
; control for disabling the loading of BIOS updates through Setup or ;
; other mechanism. ;
;-----------------------------------------------------------------------;
extrn q_bu_update:abs
extrn check_cmos_8e:near
extrn check_cmos_data:near
extrn set_cmos_item_checksum:near
bl_02:
mov ah,not_implemented ; error for invalid task
mov al,01h ; AL = 01h for Enable
cmp bh,01h
jb bl02_00 ; invalid task (input BH = 00)
jnz bl02_01 ; input BH <> 1
; input BH = 01, Enable update loading
call check_cmos_8e
mov ah,read_failure ; error for CMOS bad
jnz bl02_00 ; CMOS bad
mov ah,01h ; Enable
mov al,q_bu_update ; AH, AL = data, setup structure#
call set_cmos_item_checksum
mov bl,01h ; enable
jmp short bl02_02
bl02_01:
cmp bh,02h
jnz bl02_00 ; invalid task (input BH > 2)
; input BH = 02, Return current state
mov al,q_bu_update ; Setup structure#
call check_cmos_data
mov bl,al ; 0/1 disable/enable
bl02_02:
mov ah,success ; ok
bl02_00:
ret
;-----------------------------------------------------------------------;
; READ UPDATE DATA ;
; input : ;
; AX D042 ;
; BL 03 ;
; SI Update Number ;
; Index number (0-based) of update block to be read ;
; ES:DI Pointer to update (source) buffer ;
; ECX Bit15-00 Scratch Pad1 (Real Mode Scratch segment 64K in length)
; ECX Bit31-16 Scratch Pad2 (Real Mode Scratch segment 64K in length)
; DX Scratch Pad3 (Real Mode Scratch segment 64K in length) ;
; SS:SP Stack (32K minimum) ;
; output: ;
; CF return status ;
; NC = success ;
; CY = error ;
; AH return code ;
; AL additional OEM information ;
;-----------------------------------------------------------------------;
bl_03:
mov ah,update_num_invalid ; invalid update block number
cmp si,cgroup:update_blocks ; valid update block# ?
jae bl03_00 ; invalid update block#, error
cli
pushad
mov cx,block_length
movzx esi,si
shl esi,0bh ; 2K unit
add esi,cgroup:micro_code_start_addr
call read_bytes
popad
mov ah,success ; ok
clc
bl03_00:
ret
;-----------------------------------------------------------------------;
; SUBROUTINES ;
;-----------------------------------------------------------------------;
; READ_BYTES ;
; this routines reads the concerned NVRAM block into the given buffer. ;
; input : ;
; ES:DI Pointer to read buffer ;
; ESI absolute address of soure ;
; CX #of bytes to read ;
; output: ;
; none ;
; register destroyed : none ;
;-----------------------------------------------------------------------;
read_bytes:
push ax
mov ah, 40h
call read_sio_byte
push ax
if MKF_256K_BIOS
or al,03h
else
or al,02h
endif
call write_sio_byte
push es
push ds
pushad
push es
call go_to_flat_mode_stack
pop es
popad
pushad
movzx edi,di
rb_00:
lods ds:byte ptr [esi]
stos es:byte ptr [edi]
loop rb_00
call comeback_from_flat_mode_stack
popad
pop ds
pop es
pop ax
call write_sio_byte
pop ax
ret
;-----------------------------------------------------------------------;
; GET_PROCESSOR_UPDATE_REVISION ;
; this routine returns the update revision of the processor. ;
; input : ;
; none ;
; output: ;
; EDX update revision ;
; register destroyed : EAX, ECX, EDX ;
;-----------------------------------------------------------------------;
get_processor_update_revision:
push ebx
mov ecx,8bh ; Model specific register to be read
xor eax,eax
xor edx,edx
wrmsr ; load 0 to MSR at 8Bh
xor eax,eax
inc ax
cpuid ; CPUID will deposit an update ID value
; in 64-bit MSR at address 8Bh
mov ecx,8bh ; Model specific register to be read
rdmsr ; EDX = update revision
pop ebx
ret
;-----------------------------------------------------------------------;
_text ends
end
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