top.rpt
来自「系统实验」· RPT 代码 · 共 1,157 行 · 第 1/5 页
RPT
1,157 行
- 3 - E 24 DFFE 1 4 0 4 |LS273:11|:18
- 2 - E 08 DFFE 1 4 0 6 |LS273:11|:20
- 8 - E 15 DFFE 1 4 0 4 |LS273:11|:22
- 2 - E 24 DFFE 1 4 0 7 |LS273:11|:24
- 4 - E 05 DFFE 1 4 0 1 |LS273:12|:10
- 6 - E 11 DFFE 1 4 0 1 |LS273:12|:12
- 3 - E 11 DFFE 1 4 0 1 |LS273:12|:14
- 8 - E 11 DFFE 1 4 0 1 |LS273:12|:16
- 6 - E 22 DFFE 1 4 0 1 |LS273:12|:18
- 8 - E 22 DFFE 1 4 0 1 |LS273:12|:20
- 6 - E 20 DFFE 1 4 0 1 |LS273:12|:22
- 6 - E 23 DFFE 1 4 0 1 |LS273:12|:24
- 7 - E 22 DFFE 1 4 0 1 |LS273:13|:10
- 4 - E 22 DFFE 1 4 0 1 |LS273:13|:12
- 8 - A 11 DFFE 1 4 0 1 |LS273:13|:14
- 8 - E 19 DFFE 1 4 0 1 |LS273:13|:16
- 3 - E 22 DFFE 1 4 0 1 |LS273:13|:18
- 5 - E 22 DFFE 1 4 0 1 |LS273:13|:20
- 4 - E 19 DFFE 1 4 0 1 |LS273:13|:22
- 3 - E 19 DFFE 1 4 0 1 |LS273:13|:24
- 7 - E 05 DFFE 1 4 0 1 |LS273:14|:10
- 7 - E 13 DFFE 1 4 0 1 |LS273:14|:12
- 7 - A 11 DFFE 1 4 0 1 |LS273:14|:14
- 7 - E 12 DFFE 1 4 0 1 |LS273:14|:16
- 6 - E 13 DFFE 1 4 0 1 |LS273:14|:18
- 4 - E 13 DFFE 1 4 0 1 |LS273:14|:20
- 7 - E 20 DFFE 1 4 0 1 |LS273:14|:22
- 8 - E 23 DFFE 1 4 0 1 |LS273:14|:24
- 5 - A 04 DFFE 1 4 0 7 |LS273:16|:10
- 2 - E 06 DFFE 1 4 0 11 |LS273:16|:12
- 7 - A 04 DFFE 1 4 0 7 |LS273:16|:14
- 5 - D 03 DFFE 1 4 0 7 |LS273:16|:16
- 8 - D 02 DFFE 1 4 0 3 |LS273:16|:18
- 2 - A 04 DFFE 1 4 0 3 |LS273:16|:20
- 7 - D 02 DFFE 1 4 0 6 |LS273:16|:22
- 3 - D 05 DFFE 1 4 0 6 |LS273:16|:24
- 6 - A 02 DFFE 0 2 0 1 |LS273:23|:10
- 5 - A 02 DFFE 0 2 0 1 |LS273:23|:12
- 3 - A 02 DFFE 0 2 0 1 |LS273:23|:14
- 1 - A 02 DFFE 0 2 0 1 |LS273:23|:16
- 1 - A 10 DFFE 0 2 0 11 |LS273:23|:18
- 6 - A 24 DFFE 0 2 0 11 |LS273:23|:20
- 1 - A 16 DFFE 0 2 0 5 |LS273:23|:22
- 4 - A 02 DFFE 0 2 0 5 |LS273:23|:24
- 1 - D 01 DFFE 0 3 0 70 |MODE_CONTROL:9|M (|MODE_CONTROL:9|:38)
- 3 - D 08 OR2 s ! 0 3 0 1 |MODE_CONTROL:9|~122~1
- 1 - D 03 OR2 s 0 4 0 1 |MODE_CONTROL:9|~122~2
- 6 - D 08 AND2 0 2 0 1 |MODE_CONTROL:9|:875
- 3 - D 03 AND2 0 4 0 4 |MODE_CONTROL:9|:887
- 6 - D 03 AND2 0 4 0 2 |MODE_CONTROL:9|:911
- 2 - D 03 AND2 s ! 0 3 0 4 |MODE_CONTROL:9|~923~1
- 7 - D 03 AND2 0 4 0 3 |MODE_CONTROL:9|:935
- 4 - D 08 AND2 s 0 3 0 3 |MODE_CONTROL:9|~947~1
- 4 - D 03 AND2 0 4 0 2 |MODE_CONTROL:9|:952
- 6 - D 01 OR2 0 4 0 8 |MODE_CONTROL:9|:1154
- 3 - D 01 AND2 1 3 0 8 |MODE_CONTROL:9|:1166
- 7 - D 08 OR2 ! 0 4 0 2 |MODE_CONTROL:9|:1172
- 2 - D 01 OR2 ! 0 3 0 10 |MODE_CONTROL:9|:1178
- 1 - D 07 AND2 ! 0 2 0 4 |MODE_CONTROL:9|:1179
- 6 - D 04 AND2 0 2 0 10 |MODE_CONTROL:9|:1196
- 4 - A 03 OR2 ! 0 3 0 8 |MODE_CONTROL:9|:1216
- 1 - E 03 OR2 s 0 4 0 3 |MODE_CONTROL:9|~1267~1
- 7 - D 01 AND2 s 1 1 0 2 |MODE_CONTROL:9|~1267~2
- 4 - D 01 OR2 0 4 0 8 |MODE_CONTROL:9|:1267
- 5 - D 11 AND2 1 2 0 8 |MODE_CONTROL:9|:1275
- 2 - E 03 AND2 1 1 0 2 |MODE_CONTROL:9|:1284
- 8 - D 03 OR2 0 4 0 3 |MODE_CONTROL:9|:1295
- 1 - D 08 OR2 s ! 0 3 0 5 |MODE_CONTROL:9|~1317~1
- 8 - D 01 AND2 s ! 0 2 0 1 |MODE_CONTROL:9|~1317~2
- 5 - D 01 OR2 0 4 0 3 |MODE_CONTROL:9|:1317
- 2 - D 02 AND2 ! 0 3 0 1 |MODE_CONTROL:9|:1340
- 3 - D 02 OR2 ! 0 4 0 4 |MODE_CONTROL:9|:1362
- 4 - D 02 OR2 0 3 0 1 |MODE_CONTROL:9|:1385
- 5 - D 02 OR2 0 4 0 4 |MODE_CONTROL:9|:1408
- 6 - D 02 OR2 0 3 0 1 |MODE_CONTROL:9|:1431
- 1 - D 02 OR2 0 4 0 4 |MODE_CONTROL:9|:1454
- 5 - D 08 AND2 s 0 3 0 58 |MODE_CONTROL:9|~1464~1
- 1 - D 05 OR2 s 0 4 0 1 |MODE_CONTROL:9|~1493~1
- 4 - D 05 OR2 1 3 0 3 |MODE_CONTROL:9|:1493
- 2 - D 05 AND2 0 3 0 8 |MODE_CONTROL:9|:1517
- 5 - D 05 AND2 0 3 0 8 |MODE_CONTROL:9|:1540
- 7 - D 05 AND2 0 3 0 8 |MODE_CONTROL:9|:1563
- 8 - D 08 AND2 0 4 0 12 |MODE_CONTROL:9|:1576
- 8 - D 05 OR2 s ! 0 3 0 1 |MODE_CONTROL:9|~1607~1
- 6 - D 11 OR2 0 3 1 8 |MODE_CONTROL:9|:1607
- 2 - D 08 OR2 0 4 0 2 |MODE_CONTROL:9|:1629
- 8 - A 02 AND2 1 1 0 8 |MODE_CONTROL:9|:1635
- 7 - C 12 AND2 0 2 1 0 |MODE_CONTROL:9|:1642
- 4 - D 09 AND2 0 3 1 1 |MODE_CONTROL:9|:1650
- 1 - A 15 OR2 0 3 0 7 |MUX3:15|:172
- 3 - A 04 OR2 1 3 0 1 |MUX3:15|:178
- 5 - E 06 OR2 0 3 0 7 |MUX3:15|:184
- 4 - E 06 OR2 1 3 0 1 |MUX3:15|:187
- 2 - A 11 OR2 0 3 0 7 |MUX3:15|:193
- 6 - A 04 OR2 1 3 0 1 |MUX3:15|:196
- 1 - E 19 OR2 0 3 0 7 |MUX3:15|:202
- 5 - A 08 OR2 1 3 0 1 |MUX3:15|:205
- 2 - A 22 OR2 0 3 0 7 |MUX3:15|:211
- 4 - E 24 OR2 1 3 0 1 |MUX3:15|:214
- 6 - A 22 OR2 0 3 0 7 |MUX3:15|:220
- 1 - A 04 OR2 1 3 0 1 |MUX3:15|:223
- 2 - E 13 OR2 0 3 0 7 |MUX3:15|:229
- 6 - A 10 OR2 1 3 0 1 |MUX3:15|:232
- 7 - E 23 OR2 0 3 0 7 |MUX3:15|:238
- 5 - A 10 OR2 1 3 0 1 |MUX3:15|:241
- 8 - D 07 AND2 0 4 0 8 |MUX4:17|:113
- 4 - D 07 AND2 0 4 0 8 |MUX4:17|:122
- 6 - D 07 AND2 0 4 0 8 |MUX4:17|:131
- 2 - D 07 AND2 0 4 0 8 |MUX4:17|:140
- 5 - E 05 OR2 0 4 0 1 |MUX4:17|:304
- 6 - E 05 OR2 0 3 0 1 |MUX4:17|:310
- 1 - E 22 OR2 0 3 0 2 |MUX4:17|:316
- 1 - E 07 OR2 0 4 0 1 |MUX4:17|:325
- 8 - E 07 OR2 0 3 0 1 |MUX4:17|:328
- 1 - E 06 OR2 0 3 0 2 |MUX4:17|:331
- 1 - E 11 OR2 0 4 0 1 |MUX4:17|:340
- 1 - A 11 OR2 0 3 0 1 |MUX4:17|:343
- 3 - A 11 OR2 0 3 0 2 |MUX4:17|:346
- 6 - E 12 OR2 0 4 0 1 |MUX4:17|:355
- 8 - E 12 OR2 0 3 0 1 |MUX4:17|:358
- 2 - E 19 OR2 0 3 0 2 |MUX4:17|:361
- 7 - E 16 OR2 0 4 0 1 |MUX4:17|:370
- 3 - E 16 OR2 0 3 0 1 |MUX4:17|:373
- 2 - E 22 OR2 0 3 0 2 |MUX4:17|:376
- 6 - E 21 OR2 0 4 0 1 |MUX4:17|:385
- 7 - E 21 OR2 0 3 0 1 |MUX4:17|:388
- 3 - E 21 OR2 0 3 0 2 |MUX4:17|:391
- 5 - E 20 OR2 0 4 0 1 |MUX4:17|:400
- 8 - E 20 OR2 0 3 0 1 |MUX4:17|:403
- 1 - E 13 OR2 0 3 0 2 |MUX4:17|:406
- 1 - E 18 OR2 s 0 4 0 1 |MUX4:17|~421~1
- 1 - E 23 OR2 s 0 4 0 1 |MUX4:17|~421~2
- 2 - E 23 OR2 s 0 3 0 1 |MUX4:17|~421~3
- 4 - E 23 OR2 0 3 0 2 |MUX4:17|:421
- 4 - A 04 AND2 0 2 0 1 |PC:20|LPM_ADD_SUB:132|addcore:adder|:121
- 7 - A 10 AND2 0 3 0 1 |PC:20|LPM_ADD_SUB:132|addcore:adder|:125
- 2 - A 10 AND2 0 4 0 4 |PC:20|LPM_ADD_SUB:132|addcore:adder|:129
- 6 - A 08 AND2 0 2 0 1 |PC:20|LPM_ADD_SUB:132|addcore:adder|:133
- 7 - A 08 AND2 0 3 0 1 |PC:20|LPM_ADD_SUB:132|addcore:adder|:137
- 8 - A 08 AND2 0 4 0 1 |PC:20|LPM_ADD_SUB:132|addcore:adder|:141
- 1 - A 08 DFFE 0 4 0 1 |PC:20|qout7 (|PC:20|:20)
- 2 - A 08 DFFE 0 4 0 2 |PC:20|qout6 (|PC:20|:21)
- 3 - A 08 DFFE 0 4 0 3 |PC:20|qout5 (|PC:20|:22)
- 4 - A 08 DFFE 0 4 0 4 |PC:20|qout4 (|PC:20|:23)
- 8 - A 10 DFFE 0 4 0 2 |PC:20|qout3 (|PC:20|:24)
- 8 - A 04 DFFE 0 4 0 3 |PC:20|qout2 (|PC:20|:25)
- 3 - A 10 DFFE 0 4 0 4 |PC:20|qout1 (|PC:20|:26)
- 4 - A 10 DFFE 0 3 0 5 |PC:20|qout0 (|PC:20|:27)
- 3 - A 16 AND2 s 0 3 0 5 |ROM:34|~5639~1
- 7 - A 24 AND2 0 2 0 1 |ROM:34|:5639
- 2 - A 20 OR2 0 4 0 1 |ROM:34|:5642
- 4 - A 24 AND2 s ! 0 2 0 4 |ROM:34|~5659~1
- 3 - A 23 AND2 0 2 0 3 |ROM:34|:5659
- 5 - A 24 OR2 s 0 2 0 5 |ROM:34|~5739~1
- 8 - A 24 OR2 ! 0 2 0 5 |ROM:34|:5739
- 6 - A 23 AND2 s ! 0 2 0 3 |ROM:34|~5742~1
- 1 - A 20 AND2 0 3 0 6 |ROM:34|:5759
- 8 - A 16 OR2 s 0 3 0 3 |ROM:34|~5779~1
- 3 - A 20 OR2 ! 0 3 0 3 |ROM:34|:5779
- 1 - A 23 OR2 0 3 0 2 |ROM:34|:5784
- 2 - A 02 AND2 s ! 0 4 0 5 |ROM:34|~5799~1
- 8 - A 20 AND2 0 3 0 3 |ROM:34|:5799
- 2 - A 16 AND2 s ! 0 3 0 4 |ROM:34|~5819~1
- 3 - A 24 OR2 ! 0 3 0 4 |ROM:34|:5819
- 6 - A 16 AND2 s ! 0 3 0 5 |ROM:34|~5839~1
- 7 - A 20 OR2 ! 0 3 0 5 |ROM:34|:5839
- 5 - A 15 OR2 0 4 0 1 |ROM:34|:5842
- 4 - A 20 AND2 0 3 0 3 |ROM:34|:5859
- 6 - A 20 AND2 0 3 0 3 |ROM:34|:5879
- 2 - A 24 OR2 ! 0 3 0 3 |ROM:34|:5899
- 6 - A 15 OR2 0 4 0 1 |ROM:34|:5902
- 8 - A 23 OR2 0 4 0 2 |ROM:34|:5971
- 5 - A 23 OR2 0 4 0 1 |ROM:34|:5989
- 1 - A 24 OR2 0 4 0 1 |ROM:34|:6039
- 2 - A 15 OR2 0 4 0 1 |ROM:34|:6048
- 3 - A 15 OR2 0 4 0 1 |ROM:34|:6052
- 4 - A 23 OR2 0 4 0 1 |ROM:34|:6085
- 7 - A 23 OR2 s 0 4 0 1 |ROM:34|~6087~1
- 5 - A 16 OR2 0 4 0 1 |ROM:34|:6136
- 2 - A 23 OR2 0 4 0 2 |ROM:34|:6231
- 7 - A 16 OR2 s 0 4 0 4 |ROM:34|~6232~1
- 4 - A 16 OR2 0 3 0 1 |ROM:34|:6240
- 1 - A 19 OR2 0 3 0 1 |ROM:34|:6246
- 6 - A 13 OR2 0 4 0 1 |ROM:34|:6256
- 8 - A 15 OR2 0 2 0 1 |ROM:34|:6279
- 7 - E 06 OR2 0 3 0 1 |ROM:34|:6285
- 4 - A 13 AND2 s 0 4 0 2 |ROM:34|~6286~1
- 5 - A 21 AND2 s 0 2 0 3 |ROM:34|~6286~2
- 6 - A 11 OR2 0 3 0 1 |ROM:34|:6291
- 5 - A 13 AND2 s 0 2 0 1 |ROM:34|~6292~1
- 7 - A 15 OR2 0 3 0 1 |ROM:34|:6297
- 7 - A 22 OR2 0 3 0 1 |ROM:34|:6303
- 3 - A 22 OR2 0 3 0 1 |ROM:34|:6309
- 5 - A 20 AND2 s 0 2 0 3 |ROM:34|~6310~1
- 2 - A 13 OR2 0 2 0 1 |ROM:34|:6315
- 3 - A 13 OR2 s ! 0 2 0 3 |ROM:34|~6316~1
- 7 - A 13 AND2 s 0 2 0 3 |ROM:34|~6316~2
- 8 - A 13 OR2 0 4 0 1 |ROM:34|:6316
- 1 - A 13 OR2 0 3 0 1 |ROM:34|:6321
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\program\vhdl\risc\test\top.rpt
top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 22/ 96( 22%) 22/ 48( 45%) 33/ 48( 68%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 13/ 96( 13%) 25/ 48( 52%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
E: 52/ 96( 54%) 36/ 48( 75%) 31/ 48( 64%) 2/16( 12%) 6/16( 37%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
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