ls74.vhd

来自「系统实验」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--
ENTITY LS74 IS
PORT(
  LDFR: in std_logic;
  CY,ZI: in std_logic;
  FC,FZ: OUT std_logic
 );
END LS74;

ARCHITECTURE ONE OF LS74 IS
 BEGIN
    process(LDFR)
    BEGIN
    if (ldfr'event and ldfr='1') then
      FC<=CY;
      FZ<=ZI;
    end if;
    END process;
 END one;