allot.vhd

系统实验

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--
ENTITY ALLOT IS
PORT(
  LED: in std_logic;  --high level enable
  WR: in std_logic;
  indata: in std_logic_vector(7 downto 0);
  outbus,output: OUT std_logic_vector(7 downto 0)
 );
END ALLOT;

ARCHITECTURE ONE OF ALLOT IS
 BEGIN
    process(LED,WR)
    BEGIN
    if (LED='0' and WR='0') then
     output<=indata;
    else
        outbus<=indata;
      end if;  
    END process;
 END one;