📄 allot.rpt
字号:
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\program\vhdl\risc\test\allot.rpt
allot
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 1/ 48( 2%) 2/ 48( 4%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 1/ 96( 1%) 2/ 48( 4%) 1/ 48( 2%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 5/ 96( 5%) 0/ 48( 0%) 3/ 48( 6%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\program\vhdl\risc\test\allot.rpt
allot
** EQUATIONS **
indata0 : INPUT;
indata1 : INPUT;
indata2 : INPUT;
indata3 : INPUT;
indata4 : INPUT;
indata5 : INPUT;
indata6 : INPUT;
indata7 : INPUT;
LED : INPUT;
WR : INPUT;
-- Node name is 'outbus0'
-- Equation name is 'outbus0', type is output
outbus0 = _LC1_B20;
-- Node name is 'outbus1'
-- Equation name is 'outbus1', type is output
outbus1 = _LC1_A18;
-- Node name is 'outbus2'
-- Equation name is 'outbus2', type is output
outbus2 = _LC4_B10;
-- Node name is 'outbus3'
-- Equation name is 'outbus3', type is output
outbus3 = _LC8_A15;
-- Node name is 'outbus4'
-- Equation name is 'outbus4', type is output
outbus4 = _LC1_A5;
-- Node name is 'outbus5'
-- Equation name is 'outbus5', type is output
outbus5 = _LC7_B14;
-- Node name is 'outbus6'
-- Equation name is 'outbus6', type is output
outbus6 = _LC1_B2;
-- Node name is 'outbus7'
-- Equation name is 'outbus7', type is output
outbus7 = _LC5_A19;
-- Node name is 'output0'
-- Equation name is 'output0', type is output
output0 = _LC5_C23;
-- Node name is 'output1'
-- Equation name is 'output1', type is output
output1 = _LC1_C23;
-- Node name is 'output2'
-- Equation name is 'output2', type is output
output2 = _LC8_C23;
-- Node name is 'output3'
-- Equation name is 'output3', type is output
output3 = _LC3_C23;
-- Node name is 'output4'
-- Equation name is 'output4', type is output
output4 = _LC4_C23;
-- Node name is 'output5'
-- Equation name is 'output5', type is output
output5 = _LC7_C23;
-- Node name is 'output6'
-- Equation name is 'output6', type is output
output6 = _LC6_C23;
-- Node name is 'output7'
-- Equation name is 'output7', type is output
output7 = _LC2_C23;
-- Node name is ':158'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = LCELL( _LC5_A19);
-- Node name is ':167'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _LC1_B2);
-- Node name is ':176'
-- Equation name is '_LC7_B14', type is buried
_LC7_B14 = LCELL( _LC7_B14);
-- Node name is ':185'
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = LCELL( _LC1_A5);
-- Node name is ':194'
-- Equation name is '_LC8_A15', type is buried
_LC8_A15 = LCELL( _LC8_A15);
-- Node name is ':203'
-- Equation name is '_LC4_B10', type is buried
_LC4_B10 = LCELL( _LC4_B10);
-- Node name is ':212'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = LCELL( _LC1_A18);
-- Node name is ':221'
-- Equation name is '_LC1_B20', type is buried
_LC1_B20 = LCELL( _LC1_B20);
-- Node name is ':230'
-- Equation name is '_LC2_C23', type is buried
_LC2_C23 = LCELL( _EQ001);
_EQ001 = indata7 & !LED & !WR;
-- Node name is ':239'
-- Equation name is '_LC6_C23', type is buried
_LC6_C23 = LCELL( _EQ002);
_EQ002 = indata6 & !LED & !WR;
-- Node name is ':248'
-- Equation name is '_LC7_C23', type is buried
_LC7_C23 = LCELL( _EQ003);
_EQ003 = indata5 & !LED & !WR;
-- Node name is ':257'
-- Equation name is '_LC4_C23', type is buried
_LC4_C23 = LCELL( _EQ004);
_EQ004 = indata4 & !LED & !WR;
-- Node name is ':266'
-- Equation name is '_LC3_C23', type is buried
_LC3_C23 = LCELL( _EQ005);
_EQ005 = indata3 & !LED & !WR;
-- Node name is ':275'
-- Equation name is '_LC8_C23', type is buried
_LC8_C23 = LCELL( _EQ006);
_EQ006 = indata2 & !LED & !WR;
-- Node name is ':284'
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = LCELL( _EQ007);
_EQ007 = indata1 & !LED & !WR;
-- Node name is ':293'
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = LCELL( _EQ008);
_EQ008 = indata0 & !LED & !WR;
Project Information e:\program\vhdl\risc\test\allot.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 20,498K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -