📄 11.rpt
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- 5 - C 18 OR2 ! 0 4 0 4 |MODE_CONTROL:9|:1362
- 3 - C 20 OR2 0 3 0 1 |MODE_CONTROL:9|:1385
- 1 - C 18 OR2 0 4 0 4 |MODE_CONTROL:9|:1408
- 4 - C 20 OR2 0 3 0 1 |MODE_CONTROL:9|:1431
- 2 - C 18 OR2 0 4 0 4 |MODE_CONTROL:9|:1454
- 3 - C 19 AND2 s 0 3 0 57 |MODE_CONTROL:9|~1464~1
- 7 - C 21 OR2 s 0 4 0 1 |MODE_CONTROL:9|~1493~1
- 8 - C 19 OR2 1 3 0 3 |MODE_CONTROL:9|:1493
- 6 - C 18 AND2 0 3 0 8 |MODE_CONTROL:9|:1517
- 7 - C 18 AND2 0 3 0 8 |MODE_CONTROL:9|:1540
- 3 - C 18 AND2 0 3 0 8 |MODE_CONTROL:9|:1563
- 5 - C 19 AND2 0 3 0 12 |MODE_CONTROL:9|:1576
- 6 - C 21 OR2 s ! 0 4 0 8 |MODE_CONTROL:9|~1607~1
- 5 - A 22 AND2 1 1 0 8 |MODE_CONTROL:9|:1635
- 4 - B 22 OR2 0 4 0 7 |MUX3:15|:172
- 8 - A 23 OR2 1 3 0 1 |MUX3:15|:178
- 5 - B 20 OR2 0 4 0 7 |MUX3:15|:184
- 2 - B 20 OR2 1 3 0 1 |MUX3:15|:187
- 1 - B 24 OR2 0 4 0 7 |MUX3:15|:193
- 6 - A 23 OR2 1 3 0 1 |MUX3:15|:196
- 8 - B 21 OR2 0 4 0 7 |MUX3:15|:202
- 2 - B 21 OR2 1 3 0 1 |MUX3:15|:205
- 2 - B 23 OR2 0 4 0 7 |MUX3:15|:211
- 2 - A 23 OR2 1 3 0 1 |MUX3:15|:214
- 2 - A 22 OR2 0 4 0 7 |MUX3:15|:220
- 8 - A 20 OR2 1 3 0 1 |MUX3:15|:223
- 3 - A 24 OR2 0 4 0 7 |MUX3:15|:229
- 7 - A 20 OR2 1 3 0 1 |MUX3:15|:232
- 1 - A 15 OR2 0 4 0 7 |MUX3:15|:238
- 5 - A 20 OR2 1 3 0 1 |MUX3:15|:241
- 6 - C 23 AND2 0 4 0 8 |MUX4:17|:113
- 8 - C 23 OR2 ! 0 4 0 8 |MUX4:17|:122
- 5 - C 23 AND2 0 4 0 8 |MUX4:17|:131
- 1 - C 23 AND2 0 4 0 8 |MUX4:17|:140
- 2 - B 10 OR2 0 4 0 1 |MUX4:17|:304
- 2 - B 22 OR2 0 3 0 1 |MUX4:17|:310
- 3 - B 22 OR2 0 3 0 2 |MUX4:17|:316
- 5 - B 02 OR2 0 4 0 1 |MUX4:17|:325
- 6 - B 02 OR2 0 3 0 1 |MUX4:17|:328
- 3 - B 20 OR2 0 3 0 2 |MUX4:17|:331
- 7 - B 13 OR2 0 4 0 1 |MUX4:17|:340
- 2 - B 24 OR2 0 3 0 1 |MUX4:17|:343
- 4 - B 24 OR2 0 3 0 2 |MUX4:17|:346
- 3 - B 03 OR2 0 4 0 1 |MUX4:17|:355
- 6 - B 03 OR2 0 3 0 1 |MUX4:17|:358
- 1 - B 21 OR2 0 3 0 2 |MUX4:17|:361
- 1 - B 19 OR2 0 4 0 1 |MUX4:17|:370
- 5 - B 19 OR2 0 3 0 1 |MUX4:17|:373
- 1 - B 23 OR2 0 3 0 2 |MUX4:17|:376
- 3 - B 13 OR2 0 4 0 1 |MUX4:17|:385
- 3 - A 17 OR2 0 3 0 1 |MUX4:17|:388
- 2 - A 17 OR2 0 3 0 2 |MUX4:17|:391
- 4 - A 24 OR2 0 4 0 1 |MUX4:17|:400
- 5 - A 24 OR2 0 3 0 1 |MUX4:17|:403
- 6 - A 24 OR2 0 3 0 2 |MUX4:17|:406
- 2 - A 15 OR2 s 0 4 0 1 |MUX4:17|~421~1
- 3 - A 15 OR2 s 0 4 0 1 |MUX4:17|~421~2
- 4 - A 15 OR2 s 0 3 0 1 |MUX4:17|~421~3
- 5 - A 15 OR2 0 3 0 2 |MUX4:17|:421
- 1 - A 20 AND2 0 2 0 3 |PC:20|LPM_ADD_SUB:132|addcore:adder|:121
- 7 - A 23 AND2 0 2 0 1 |PC:20|LPM_ADD_SUB:132|addcore:adder|:125
- 4 - A 23 AND2 0 3 0 4 |PC:20|LPM_ADD_SUB:132|addcore:adder|:129
- 3 - A 18 AND2 0 2 0 1 |PC:20|LPM_ADD_SUB:132|addcore:adder|:133
- 6 - A 18 AND2 0 3 0 1 |PC:20|LPM_ADD_SUB:132|addcore:adder|:137
- 5 - A 18 AND2 0 4 0 1 |PC:20|LPM_ADD_SUB:132|addcore:adder|:141
- 4 - A 18 DFFE 0 4 0 1 |PC:20|qout7 (|PC:20|:20)
- 1 - A 18 DFFE 0 4 0 2 |PC:20|qout6 (|PC:20|:21)
- 2 - A 18 DFFE 0 4 0 3 |PC:20|qout5 (|PC:20|:22)
- 8 - A 18 DFFE 0 4 0 4 |PC:20|qout4 (|PC:20|:23)
- 3 - A 23 DFFE 0 4 0 2 |PC:20|qout3 (|PC:20|:24)
- 3 - A 20 DFFE 0 4 0 3 |PC:20|qout2 (|PC:20|:25)
- 4 - A 20 DFFE 0 4 0 2 |PC:20|qout1 (|PC:20|:26)
- 6 - A 20 DFFE 0 3 0 3 |PC:20|qout0 (|PC:20|:27)
- 4 - A 13 OR2 s ! 0 2 0 3 |ROM:34|~1951~1
- 7 - A 14 AND2 s 0 3 0 1 |ROM:34|~2011~1
- 2 - A 14 AND2 s ! 0 3 0 3 |ROM:34|~2011~2
- 6 - A 13 AND2 0 3 0 2 |ROM:34|:2174
- 2 - A 13 OR2 0 4 0 1 |ROM:34|:2198
- 6 - B 22 OR2 0 2 0 1 |ROM:34|:2221
- 6 - B 20 OR2 0 2 0 1 |ROM:34|:2227
- 6 - B 24 OR2 0 2 0 1 |ROM:34|:2233
- 4 - B 21 OR2 0 2 0 1 |ROM:34|:2239
- 5 - B 23 OR2 0 2 0 1 |ROM:34|:2245
- 3 - A 13 AND2 s 0 3 0 1 |ROM:34|~2251~1
- 4 - A 22 OR2 0 3 0 1 |ROM:34|:2251
- 7 - A 13 OR2 s 0 3 0 1 |ROM:34|~2252~1
- 3 - A 22 OR2 0 3 0 1 |ROM:34|:2257
- 5 - A 13 OR2 s 0 4 0 1 |ROM:34|~2258~1
- 8 - A 13 OR2 0 3 0 1 |ROM:34|:2263
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\program\vhdl\risc\test\11.rpt
11
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 43/ 96( 44%) 0/ 48( 0%) 18/ 48( 37%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 67/ 96( 69%) 5/ 48( 10%) 20/ 48( 41%) 2/16( 12%) 5/16( 31%) 0/16( 0%)
C: 30/ 96( 31%) 0/ 48( 0%) 6/ 48( 12%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 7/24( 29%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 5/24( 20%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 9/24( 37%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\program\vhdl\risc\test\11.rpt
11
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 Q
LCELL 8 |MODE_CONTROL:9|:1635
LCELL 8 |MODE_CONTROL:9|:1563
LCELL 8 |MODE_CONTROL:9|:1540
LCELL 8 |MODE_CONTROL:9|:1517
DFF 8 |COUNTER:1|:9
LCELL 8 |MODE_CONTROL:9|:1275
LCELL 8 |MODE_CONTROL:9|:1267
LCELL 8 |MODE_CONTROL:9|:1166
LCELL 8 |MODE_CONTROL:9|:1154
LCELL 2 |MODE_CONTROL:9|:1284
Device-Specific Information: e:\program\vhdl\risc\test\11.rpt
11
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 15 CLR
Device-Specific Information: e:\program\vhdl\risc\test\11.rpt
11
** EQUATIONS **
CLR : INPUT;
in20 : INPUT;
in21 : INPUT;
in22 : INPUT;
in23 : INPUT;
in24 : INPUT;
in25 : INPUT;
in26 : INPUT;
in27 : INPUT;
Q : INPUT;
-- Node name is 'output0'
-- Equation name is 'output0', type is output
output0 = _LC7_A15;
-- Node name is 'output1'
-- Equation name is 'output1', type is output
output1 = _LC1_A24;
-- Node name is 'output2'
-- Equation name is 'output2', type is output
output2 = _LC8_A22;
-- Node name is 'output3'
-- Equation name is 'output3', type is output
output3 = _LC3_B23;
-- Node name is 'output4'
-- Equation name is 'output4', type is output
output4 = _LC5_B21;
-- Node name is 'output5'
-- Equation name is 'output5', type is output
output5 = _LC3_B24;
-- Node name is 'output6'
-- Equation name is 'output6', type is output
output6 = _LC7_B20;
-- Node name is 'output7'
-- Equation name is 'output7', type is output
output7 = _LC1_B22;
-- Node name is '|ALLOT:2|:35'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = LCELL( _EQ001);
_EQ001 = _LC2_C13 & !_LC5_C13 & _LC8_C22 & Q;
-- Node name is '|ALLOT:2|:109'
-- Equation name is '_LC1_B22', type is buried
_LC1_B22 = LCELL( _EQ002);
_EQ002 = _LC1_B22 & _LC1_C13
# !_LC1_C13 & _LC3_B22;
-- Node name is '|ALLOT:2|:115'
-- Equation name is '_LC7_B20', type is buried
_LC7_B20 = LCELL( _EQ003);
_EQ003 = _LC1_C13 & _LC7_B20
# !_LC1_C13 & _LC3_B20;
-- Node name is '|ALLOT:2|:121'
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ004);
_EQ004 = _LC1_C13 & _LC3_B24
# !_LC1_C13 & _LC4_B24;
-- Node name is '|ALLOT:2|:127'
-- Equation name is '_LC5_B21', type is buried
_LC5_B21 = LCELL( _EQ005);
_EQ005 = _LC1_C13 & _LC5_B21
# _LC1_B21 & !_LC1_C13;
-- Node name is '|ALLOT:2|:133'
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = LCELL( _EQ006);
_EQ006 = _LC1_C13 & _LC3_B23
# _LC1_B23 & !_LC1_C13;
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