📄 11.rpt
字号:
Total flipflops required: 73
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 22/ 576 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 0 8 7 0 8 0 7 8 8 70/0
B: 8 8 7 2 7 0 0 8 0 2 0 2 0 4 8 8 8 8 7 4 8 8 8 7 8 130/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 2 0 0 0 8 8 7 8 7 5 0 53/0
Total: 8 8 7 2 7 0 0 8 0 2 0 2 0 20 18 16 8 16 22 12 23 16 22 20 16 253/0
Device-Specific Information: e:\program\vhdl\risc\test\11.rpt
11
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
38 - - - -- INPUT G ^ 0 0 0 0 CLR
40 - - - -- INPUT ^ 0 0 0 7 in20
89 - - - -- INPUT ^ 0 0 0 7 in21
91 - - - -- INPUT ^ 0 0 0 7 in22
90 - - - -- INPUT ^ 0 0 0 7 in23
65 - - B -- INPUT ^ 0 0 0 7 in24
98 - - - 24 INPUT ^ 0 0 0 7 in25
63 - - B -- INPUT ^ 0 0 0 7 in26
97 - - - 23 INPUT ^ 0 0 0 7 in27
39 - - - -- INPUT G ^ 0 0 0 7 Q
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\program\vhdl\risc\test\11.rpt
11
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - A -- OUTPUT 0 1 0 0 output0
6 - - A -- OUTPUT 0 1 0 0 output1
10 - - A -- OUTPUT 0 1 0 0 output2
14 - - B -- OUTPUT 0 1 0 0 output3
15 - - B -- OUTPUT 0 1 0 0 output4
64 - - B -- OUTPUT 0 1 0 0 output5
16 - - B -- OUTPUT 0 1 0 0 output6
13 - - B -- OUTPUT 0 1 0 0 output7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\program\vhdl\risc\test\11.rpt
11
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 13 AND2 1 3 0 16 |ALLOT:2|:35
- 1 - B 22 OR2 0 2 1 0 |ALLOT:2|:109
- 7 - B 20 OR2 0 2 1 0 |ALLOT:2|:115
- 3 - B 24 OR2 0 2 1 0 |ALLOT:2|:121
- 5 - B 21 OR2 0 2 1 0 |ALLOT:2|:127
- 3 - B 23 OR2 0 2 1 0 |ALLOT:2|:133
- 8 - A 22 OR2 0 2 1 0 |ALLOT:2|:139
- 1 - A 24 OR2 0 2 1 0 |ALLOT:2|:145
- 7 - A 15 OR2 0 2 1 0 |ALLOT:2|:151
- 5 - B 22 OR2 0 2 0 1 |ALLOT:2|:157
- 4 - B 20 OR2 0 2 0 1 |ALLOT:2|:163
- 5 - B 24 OR2 0 2 0 1 |ALLOT:2|:169
- 3 - B 21 OR2 0 2 0 1 |ALLOT:2|:175
- 4 - B 23 OR2 0 2 0 1 |ALLOT:2|:181
- 1 - A 22 OR2 0 2 0 1 |ALLOT:2|:187
- 7 - A 24 OR2 0 2 0 1 |ALLOT:2|:193
- 6 - A 15 OR2 0 2 0 1 |ALLOT:2|:199
- 6 - B 14 OR2 0 4 0 2 |ALU:27|LPM_ADD_SUB:141|addcore:adder|pcarry1
- 2 - B 15 OR2 0 3 0 2 |ALU:27|LPM_ADD_SUB:141|addcore:adder|pcarry2
- 8 - B 15 OR2 0 3 0 2 |ALU:27|LPM_ADD_SUB:141|addcore:adder|pcarry3
- 4 - B 01 OR2 0 3 0 2 |ALU:27|LPM_ADD_SUB:141|addcore:adder|pcarry4
- 2 - B 01 OR2 0 3 0 2 |ALU:27|LPM_ADD_SUB:141|addcore:adder|pcarry5
- 5 - B 14 AND2 0 2 0 1 |ALU:27|LPM_ADD_SUB:141|addcore:adder|:114
- 8 - B 01 OR2 0 3 0 1 |ALU:27|LPM_ADD_SUB:141|addcore:adder|:160
- 7 - B 05 OR2 0 4 0 1 |ALU:27|LPM_ADD_SUB:141|addcore:adder|:162
- 7 - B 14 OR2 0 4 0 2 |ALU:27|LPM_ADD_SUB:236|addcore:adder|pcarry1
- 4 - B 15 OR2 0 3 0 2 |ALU:27|LPM_ADD_SUB:236|addcore:adder|pcarry2
- 3 - B 15 OR2 0 3 0 2 |ALU:27|LPM_ADD_SUB:236|addcore:adder|pcarry3
- 1 - B 08 OR2 0 3 0 2 |ALU:27|LPM_ADD_SUB:236|addcore:adder|pcarry4
- 7 - B 08 OR2 0 3 0 2 |ALU:27|LPM_ADD_SUB:236|addcore:adder|pcarry5
- 3 - B 05 OR2 0 3 0 1 |ALU:27|LPM_ADD_SUB:236|addcore:adder|pcarry6
- 5 - B 18 AND2 0 3 0 4 |ALU:27|LPM_ADD_SUB:396|addcore:adder|:125
- 3 - B 08 AND2 0 2 0 1 |ALU:27|LPM_ADD_SUB:396|addcore:adder|:129
- 4 - B 08 AND2 0 4 0 2 |ALU:27|LPM_ADD_SUB:396|addcore:adder|:137
- 7 - B 03 AND2 0 2 0 7 |ALU:27|:92
- 7 - B 16 OR2 0 3 0 1 |ALU:27|:261
- 1 - B 05 OR2 ! 0 3 0 2 |ALU:27|:266
- 7 - B 01 OR2 ! 0 3 0 1 |ALU:27|:271
- 3 - B 01 OR2 ! 0 4 0 1 |ALU:27|:276
- 1 - B 01 OR2 ! 0 2 0 1 |ALU:27|:282
- 6 - B 18 OR2 ! 0 4 0 1 |ALU:27|:283
- 8 - B 14 OR2 ! 0 4 0 1 |ALU:27|:291
- 6 - B 05 OR2 ! 0 2 0 1 |ALU:27|:315
- 1 - B 02 OR2 ! 0 2 0 3 |ALU:27|:316
- 6 - B 01 OR2 ! 0 2 0 3 |ALU:27|:318
- 1 - B 15 OR2 ! 0 2 0 4 |ALU:27|:319
- 2 - B 18 OR2 ! 0 2 0 3 |ALU:27|:320
- 1 - B 14 OR2 ! 0 2 0 3 |ALU:27|:321
- 4 - B 05 OR2 0 4 0 1 |ALU:27|:453
- 5 - B 05 OR2 0 4 0 1 |ALU:27|:454
- 2 - B 05 OR2 0 4 0 1 |ALU:27|:458
- 3 - B 02 OR2 0 4 0 1 |ALU:27|:467
- 2 - B 02 OR2 0 3 0 1 |ALU:27|:469
- 4 - B 02 OR2 0 4 0 1 |ALU:27|:470
- 2 - B 08 OR2 0 4 0 1 |ALU:27|:480
- 5 - B 08 OR2 0 4 0 1 |ALU:27|:481
- 8 - B 08 OR2 0 4 0 1 |ALU:27|:482
- 1 - B 03 OR2 0 4 0 1 |ALU:27|:491
- 6 - B 08 OR2 0 4 0 1 |ALU:27|:493
- 2 - B 03 OR2 0 4 0 1 |ALU:27|:494
- 7 - B 15 OR2 0 4 0 1 |ALU:27|:503
- 5 - B 15 OR2 0 3 0 1 |ALU:27|:505
- 6 - B 15 OR2 0 4 0 1 |ALU:27|:506
- 7 - B 18 OR2 0 4 0 1 |ALU:27|:515
- 3 - B 18 OR2 0 4 0 1 |ALU:27|:517
- 4 - B 18 OR2 0 4 0 1 |ALU:27|:518
- 4 - B 14 OR2 0 4 0 1 |ALU:27|:527
- 2 - B 14 OR2 0 4 0 1 |ALU:27|:528
- 3 - B 14 OR2 0 4 0 1 |ALU:27|:530
- 5 - B 01 OR2 s 0 4 0 1 |ALU:27|~568~1
- 1 - B 18 OR2 s 0 4 0 1 |ALU:27|~568~2
- 1 - B 16 OR2 s 0 4 0 1 |ALU:27|~568~3
- 7 - C 22 DFFE + 0 2 0 3 |COUNTER:1|:3
- 6 - C 22 DFFE + 0 2 0 2 |COUNTER:1|:5
- 8 - C 22 DFFE + 0 2 0 6 |COUNTER:1|:7
- 2 - C 22 DFFE + 0 2 0 8 |COUNTER:1|:9
- 4 - C 22 DFFE + 0 1 0 4 |COUNTER:1|X1 (|COUNTER:1|:11)
- 3 - C 22 DFFE + 0 0 0 5 |COUNTER:1|X0 (|COUNTER:1|:12)
- 8 - B 17 DFFE 0 3 0 1 |LS74:19|:4
- 7 - B 17 DFFE 0 5 0 1 |LS74:19|:6
- 6 - B 16 DFFE 1 4 0 5 |LS273:10|:10
- 8 - B 04 DFFE 1 4 0 6 |LS273:10|:12
- 3 - B 16 DFFE 1 4 0 8 |LS273:10|:14
- 6 - B 12 DFFE 1 4 0 7 |LS273:10|:16
- 8 - B 23 DFFE 1 4 0 8 |LS273:10|:18
- 2 - B 16 DFFE 1 4 0 6 |LS273:10|:20
- 8 - B 16 DFFE 1 4 0 7 |LS273:10|:22
- 4 - C 14 DFFE 1 4 0 10 |LS273:10|:24
- 4 - B 16 DFFE 1 4 0 4 |LS273:11|:10
- 4 - B 04 DFFE 1 4 0 4 |LS273:11|:12
- 5 - B 16 DFFE 1 4 0 6 |LS273:11|:14
- 6 - B 21 DFFE 1 4 0 4 |LS273:11|:16
- 8 - C 20 DFFE 1 4 0 4 |LS273:11|:18
- 1 - C 20 DFFE 1 4 0 4 |LS273:11|:20
- 2 - A 24 DFFE 1 4 0 4 |LS273:11|:22
- 1 - C 14 DFFE 1 4 0 7 |LS273:11|:24
- 1 - B 10 DFFE 1 4 0 1 |LS273:12|:10
- 7 - B 02 DFFE 1 4 0 1 |LS273:12|:12
- 2 - B 13 DFFE 1 4 0 1 |LS273:12|:14
- 4 - B 03 DFFE 1 4 0 1 |LS273:12|:16
- 2 - B 19 DFFE 1 4 0 1 |LS273:12|:18
- 1 - B 13 DFFE 1 4 0 1 |LS273:12|:20
- 8 - A 24 DFFE 1 4 0 1 |LS273:12|:22
- 8 - A 15 DFFE 1 4 0 1 |LS273:12|:24
- 8 - B 22 DFFE 1 4 0 1 |LS273:13|:10
- 8 - B 20 DFFE 1 4 0 1 |LS273:13|:12
- 8 - B 24 DFFE 1 4 0 1 |LS273:13|:14
- 7 - B 21 DFFE 1 4 0 1 |LS273:13|:16
- 6 - B 23 DFFE 1 4 0 1 |LS273:13|:18
- 7 - A 17 DFFE 1 4 0 1 |LS273:13|:20
- 8 - A 17 DFFE 1 4 0 1 |LS273:13|:22
- 1 - A 17 DFFE 1 4 0 1 |LS273:13|:24
- 7 - B 22 DFFE 1 4 0 1 |LS273:14|:10
- 8 - B 02 DFFE 1 4 0 1 |LS273:14|:12
- 7 - B 24 DFFE 1 4 0 1 |LS273:14|:14
- 5 - B 03 DFFE 1 4 0 1 |LS273:14|:16
- 3 - B 19 DFFE 1 4 0 1 |LS273:14|:18
- 5 - A 17 DFFE 1 4 0 1 |LS273:14|:20
- 6 - A 17 DFFE 1 4 0 1 |LS273:14|:22
- 4 - A 17 DFFE 1 4 0 1 |LS273:14|:24
- 1 - A 23 DFFE 1 4 0 8 |LS273:16|:10
- 1 - B 20 DFFE 1 4 0 10 |LS273:16|:12
- 5 - A 23 DFFE 1 4 0 8 |LS273:16|:14
- 7 - B 12 DFFE 1 4 0 8 |LS273:16|:16
- 6 - C 20 DFFE 1 4 0 3 |LS273:16|:18
- 2 - C 20 DFFE 1 4 0 3 |LS273:16|:20
- 8 - C 18 DFFE 1 4 0 6 |LS273:16|:22
- 4 - C 18 DFFE 1 4 0 6 |LS273:16|:24
- 1 - A 14 DFFE 0 2 0 1 |LS273:23|:10
- 8 - A 14 DFFE 0 2 0 1 |LS273:23|:12
- 6 - A 14 DFFE 0 2 0 1 |LS273:23|:14
- 4 - A 14 DFFE 0 2 0 1 |LS273:23|:16
- 3 - A 14 DFFE 0 2 0 1 |LS273:23|:18
- 1 - A 13 DFFE 0 2 0 5 |LS273:23|:20
- 5 - A 14 DFFE 0 2 0 3 |LS273:23|:22
- 2 - A 20 DFFE 0 2 0 2 |LS273:23|:24
- 5 - C 13 DFFE 0 3 0 81 |MODE_CONTROL:9|M (|MODE_CONTROL:9|:38)
- 4 - B 17 OR2 s ! 0 2 0 1 |MODE_CONTROL:9|~122~1
- 7 - C 13 OR2 s 0 4 0 1 |MODE_CONTROL:9|~122~2
- 3 - B 17 AND2 0 4 0 2 |MODE_CONTROL:9|:875
- 8 - C 13 AND2 0 4 0 4 |MODE_CONTROL:9|:887
- 2 - B 17 AND2 0 4 0 2 |MODE_CONTROL:9|:911
- 4 - C 19 AND2 0 4 0 2 |MODE_CONTROL:9|:923
- 2 - C 19 AND2 0 4 0 3 |MODE_CONTROL:9|:935
- 1 - C 19 AND2 s 0 3 0 3 |MODE_CONTROL:9|~947~1
- 2 - C 13 AND2 0 4 0 2 |MODE_CONTROL:9|:952
- 2 - C 21 AND2 s 1 1 0 2 |MODE_CONTROL:9|~1154~1
- 5 - C 21 OR2 0 4 0 8 |MODE_CONTROL:9|:1154
- 7 - C 19 OR2 0 3 0 5 |MODE_CONTROL:9|:1158
- 8 - C 21 AND2 1 3 0 8 |MODE_CONTROL:9|:1166
- 6 - C 19 OR2 ! 0 4 0 2 |MODE_CONTROL:9|:1172
- 4 - C 21 OR2 ! 0 3 0 10 |MODE_CONTROL:9|:1178
- 2 - C 23 AND2 ! 0 2 0 4 |MODE_CONTROL:9|:1179
- 1 - B 17 OR2 s ! 0 4 0 7 |MODE_CONTROL:9|~1196~1
- 6 - A 22 AND2 0 2 0 7 |MODE_CONTROL:9|:1196
- 1 - C 21 OR2 ! 0 3 0 8 |MODE_CONTROL:9|:1216
- 5 - B 17 OR2 s 0 4 0 3 |MODE_CONTROL:9|~1267~1
- 3 - C 21 OR2 0 4 0 8 |MODE_CONTROL:9|:1267
- 1 - C 22 AND2 1 2 0 8 |MODE_CONTROL:9|:1275
- 6 - B 17 AND2 1 1 0 2 |MODE_CONTROL:9|:1284
- 3 - C 13 OR2 0 4 0 3 |MODE_CONTROL:9|:1295
- 4 - C 13 AND2 s ! 0 2 0 1 |MODE_CONTROL:9|~1317~1
- 6 - C 13 OR2 0 4 0 3 |MODE_CONTROL:9|:1317
- 5 - C 20 AND2 ! 0 3 0 1 |MODE_CONTROL:9|:1340
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