f020.h

CYGNAL单片机

sfr at 0xF0 B       ; /* B REGISTER                                              */
sfr at 0xF1 SCON1   ; /* SERIAL PORT 1 CONTROL                                   */
sfr at 0xF2 SBUF1   ; /* SERAIL PORT 1 DATA                                      */
sfr at 0xF3 SADDR1  ; /* SERAIL PORT 1                                           */ 
sfr at 0xF4 TL4     ; /* TIMER 4 DATA - LOW BYTE                                 */
sfr at 0xF5 TH4     ; /* TIMER 4 DATA - HIGH BYTE                                */
sfr at 0xF6 EIP1    ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1                  */
sfr at 0xF7 EIP2    ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2                  */
sfr at 0xF8 SPI0CN  ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL                   */ 
sfr at 0xF9 PCA0H   ; /* PCA 0 TIMER - HIGH BYTE                                 */
sfr at 0xFA PCA0CPH0; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
sfr at 0xFB PCA0CPH1; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
sfr at 0xFC PCA0CPH2; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
sfr at 0xFD PCA0CPH3; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
sfr at 0xFE PCA0CPH4; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */ 
sfr at 0xFF WDTCN   ; /* WATCHDOG TIMER CONTROL                                  */
    
   
/*  BIT Registers  */

/*  TCON  0x88 */
sbit at 0x88 IT0;              /* EXT. INTERRUPT 0 TYPE      */
sbit at 0x89 IE0;              /* EXT. INTERRUPT 0 EDGE FLAG */
sbit at 0x8A IT1;              /* EXT. INTERRUPT 1 TYPE      */
sbit at 0x8B IE1;              /* EXT. INTERRUPT 1 EDGE FLAG */
sbit at 0x8C TR0;              /* TIMER 0 ON/OFF CONTROL     */
sbit at 0x8D TF0;              /* TIMER 0 OVERFLOW FLAG      */
sbit at 0x8E TR1;              /* TIMER 1 ON/OFF CONTROL     */
sbit at 0x8F TF1;              /* TIMER 1 OVERFLOW FLAG      */

/*  SCON0  0x98 */
sbit at 0x98 RI0 ;             /* RECEIVE INTERRUPT FLAG              */ 
sbit at 0x99 TI0 ;             /* TRANSMIT INTERRUPT FLAG             */
sbit at 0x9A RB80;             /* RECEIVE BIT 8                       */
sbit at 0x9B TB80;             /* TRANSMIT BIT 8                      */
sbit at 0x9C REN0;             /* RECEIVE ENABLE                      */
sbit at 0x9D SM20;             /* MULTIPROCESSOR COMMUNICATION ENABLE */
sbit at 0x9E SM10;             /* SERIAL MODE CONTROL BIT 1           */
sbit at 0x9F SM00;             /* SERIAL MODE CONTROL BIT 0           */

/*  IE  0xA8 */
sbit at 0xA8 EX0;              /* EXTERNAL INTERRUPT 0 ENABLE  */  
sbit at 0xA9 ET0;              /* TIMER 0 INTERRUPT ENABLE     */         
sbit at 0xAA EX1;              /* EXTERNAL INTERRUPT 1 ENABLE  */  
sbit at 0xAB ET1;              /* TIMER 1 INTERRUPT ENABLE     */ 
sbit at 0xAC ES0;              /* UART0 INTERRUPT ENABLE       */
sbit at 0xAD ET2;              /* TIMER 2 INTERRUPT ENABLE     */
sbit at 0xAF EA;               /* GLOBAL INTERRUPT ENABLE      */ 

/*  IP  0xB8 */
sbit at 0xB8 PX0;              /* EXTERNAL INTERRUPT 0 PRIORITY */  
sbit at 0xB9 PT0;              /* TIMER 0 PRIORITY              */
sbit at 0xBA PX1;              /* EXTERNAL INTERRUPT 1 PRIORITY */
sbit at 0xBB PT1;              /* TIMER 1 PRIORITY              */
sbit at 0xBC PS0;              /* SERIAL PORT PRIORITY          */
sbit at 0xBD PT2;              /* TIMER 2 PRIORITY              */ 

/* SMB0CN 0xC0 */
sbit at 0xC0 SMBTOE ;          /* SMBUS 0 TIMEOUT ENABLE          */
sbit at 0xC1 SMBFTE ;          /* SMBUS 0 FREE TIMER ENABLE       */
sbit at 0xC2 AA     ;          /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
sbit at 0xC3 SI     ;          /* SMBUS 0 INTERRUPT PENDING FLAG  */
sbit at 0xC4 STO    ;          /* SMBUS 0 STOP FLAG               */
sbit at 0xC5 STA    ;          /* SMBUS 0 START FLAG              */
sbit at 0xC6 ENSMB  ;          /* SMBUS 0 ENABLE                  */
sbit at 0xC7 BUSY   ;          /* SMBUS 0 BUSY                    */


/*  T2CON  0xC8 */
sbit at 0xC8 CPRL2 ;           /* CAPTURE OR RELOAD SELECT     */
sbit at 0xC9 CT2   ;           /* TIMER OR COUNTER SELECT      */
sbit at 0xCA TR2   ;           /* TIMER 2 ON/OFF CONTROL       */
sbit at 0xCB EXEN2 ;           /* TIMER 2 EXTERNAL ENABLE FLAG */ 
sbit at 0xCC TCLK0 ;           /* UART0 TX CLOCK SOURCE        */
sbit at 0xCD RCLK0 ;           /* UART0 RX CLOCK SOURCE        */
sbit at 0xCE EXF2  ;           /* EXTERNAL FLAG                */
sbit at 0xCF TF2   ;           /* TIMER 2 OVERFLOW FLAG        */

/*  PSW 0xD0 */
sbit at 0xD0 P     ;           /* ACCUMULATOR PARITY FLAG */
sbit at 0xD1 F1    ;           /* USER FLAG 1             */
sbit at 0xD2 OV    ;           /* OVERFLOW FLAG           */
sbit at 0xD3 RS0   ;           /* REGISTER BANK SELECT 0  */
sbit at 0xD4 RS1   ;           /* REGISTER BANK SELECT 1  */
sbit at 0xD5 F0    ;           /* USER FLAG 0             */
sbit at 0xD6 AC    ;           /* AUXILIARY CARRY FLAG    */
sbit at 0xD7 CY    ;           /* CARRY FLAG              */ 

/* PCA0CN D8H */
sbit at 0xD8 CCF0  ;           /* PCA 0 MODULE 0 INTERRUPT FLAG */
sbit at 0xD9 CCF1  ;           /* PCA 0 MODULE 1 INTERRUPT FLAG */
sbit at 0xDA CCF2  ;           /* PCA 0 MODULE 2 INTERRUPT FLAG */
sbit at 0xDB CCF3  ;           /* PCA 0 MODULE 3 INTERRUPT FLAG */
sbit at 0xDC CCF4  ;           /* PCA 0 MODULE 4 INTERRUPT FLAG */
sbit at 0xDE CR    ;           /* PCA 0 COUNTER RUN CONTROL BIT */
sbit at 0xDF CF    ;           /* PCA 0 COUNTER OVERFLOW FLAG   */

/* ADC0CN E8H */
sbit at 0xE8 AD0LJST   ;       /* ADC 0 RIGHT JUSTIFY DATA BIT              */
sbit at 0xE9 AD0WINT   ;       /* ADC 0 WINDOW COMPARE INTERRUPT FLAG       */
sbit at 0xEA AD0CM0    ;       /* ADC 0 START OF CONVERSION MODE BIT 0      */
sbit at 0xEB AD0CM1    ;       /* ADC 0 START OF CONVERSION MODE BIT 1      */
sbit at 0xEC AD0BUSY   ;       /* ADC 0 BUSY FLAG                           */
sbit at 0xED AD0INT    ;       /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
sbit at 0xEE AD0TM     ;       /* ADC 0 TRACK MODE                          */
sbit at 0xEF AD0EN     ;       /* ADC 0 ENABLE                              */

/* SPI0CN F8H */
sbit at 0xF8 SPIEN    ;        /* SPI 0 SPI ENABLE           */   
sbit at 0xF9 MSTEN    ;        /* SPI 0 MASTER ENABLE        */
sbit at 0xFA SLVSEL   ;        /* SPI 0 SLAVE SELECT         */
sbit at 0xFB TXBSY    ;        /* SPI 0 TX BUSY FLAG         */
sbit at 0xFC RXOVRN   ;        /* SPI 0 RX OVERRUN FLAG      */
sbit at 0xFD MODF     ;        /* SPI 0 MODE FAULT FLAG      */
sbit at 0xFE WCOL     ;        /* SPI 0 WRITE COLLISION FLAG */
sbit at 0xFF SPIF     ;        /* SPI 0 INTERRUPT FLAG       */