📄 f020.h
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//------------------------------------------------------------------------------------
// C8051F020.H
//------------------------------------------------------------------------------------
//
// Description: Register/bit definitions for the C8051F02x product family.
// Target: C8051F02x
// DATE: 7 JUN 04
// Tool chain: SDCC 'c'
// Revision: 1.0
//
/* BYTE Registers */
sfr at 0x80 P0 ; /* PORT 0 */
sfr at 0x81 SP ; /* STACK POINTER */
sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
sfr at 0x84 P4 ; /* PORT 4 */
sfr at 0x85 P5 ; /* PORT 5 */
sfr at 0x86 P6 ; /* PORT 6 */
sfr at 0x87 PCON ; /* POWER CONTROL */
sfr at 0x88 TCON ; /* TIMER CONTROL */
sfr at 0x89 TMOD ; /* TIMER MODE */
sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
sfr at 0x8E CKCON ; /* CLOCK CONTROL */
sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
sfr at 0x90 P1 ; /* PORT 1 */
sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */
sfr at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
sfr at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */
sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */
sfr at 0x96 P7 ; /* PORT 7 */
sfr at 0x98 SCON0 ; /* SERIAL PORT 0 CONTROL */
sfr at 0x99 SBUF0 ; /* SERIAL PORT 0 BUFFER */
sfr at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
sfr at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
sfr at 0x9C ADC1 ; /* ADC 1 DATA */
sfr at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
sfr at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */
sfr at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */
sfr at 0xA0 P2 ; /* PORT 2 */
sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
sfr at 0xA3 EMI0CF ; /* EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION */
sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
sfr at 0xA9 SADDR0 ; /* SERIAL PORT 0 SLAVE ADDRESS */
sfr at 0xAA ADC1CN ; /* ADC 1 CONTROL */
sfr at 0xAB ADC1CF ; /* ADC 1 ANALOG MUX CONFIGURATION */
sfr at 0xAC AMX1SL ; /* ADC 1 ANALOG MUX CHANNEL SELECT */
sfr at 0xAD P3IF ; /* PORT 3 EXTERNAL INTERRUPT FLAGS */
sfr at 0xAE SADEN1 ; /* SERIAL PORT 1 SLAVE ADDRESS MASK */
sfr at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
sfr at 0xB0 P3 ; /* PORT 3 */
sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
sfr at 0xB5 P74OUT ; /* PORTS 4 - 7 OUTPUT MODE */
sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
sfr at 0xB7 FLACL ; /* FLASH ACESS LIMIT */
sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
sfr at 0xB9 SADEN0 ; /* SERIAL PORT 0 SLAVE ADDRESS MASK */
sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
sfr at 0xBD P1MDIN ; /* PORT 1 INPUT MODE */
sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
sfr at 0xC9 T4CON ; /* TIMER 4 CONTROL */
sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
sfr at 0xD5 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
sfr at 0xD6 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
sfr at 0xD7 DAC1CN ; /* DAC 1 CONTROL */
sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
sfr at 0xDA PCA0CPM0; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
sfr at 0xDB PCA0CPM1; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
sfr at 0xDC PCA0CPM2; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
sfr at 0xDD PCA0CPM3; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
sfr at 0xDE PCA0CPM4; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
sfr at 0xE0 ACC ; /* ACCUMULATOR */
sfr at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
sfr at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
sfr at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
sfr at 0xE4 RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
sfr at 0xE5 RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
sfr at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
sfr at 0xEA PCA0CPL0; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
sfr at 0xEB PCA0CPL1; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
sfr at 0xEC PCA0CPL2; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
sfr at 0xED PCA0CPL3; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
sfr at 0xEE PCA0CPL4; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
sfr at 0xEF RSTSRC ; /* RESET SOURCE */
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