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eb55评估板例程 for ads

<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
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<a name="US_IDR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> US_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>US2</b> <i><a href="AT91M55800A_h.html#AT91C_US2_IDR">AT91C_US2_IDR</a></i> 0xFFFC800C</font><font size="-2"><li><b>US1</b> <i><a href="AT91M55800A_h.html#AT91C_US1_IDR">AT91C_US1_IDR</a></i> 0xFFFC400C</font><font size="-2"><li><b>US0</b> <i><a href="AT91M55800A_h.html#AT91C_US0_IDR">AT91C_US0_IDR</a></i> 0xFFFC000C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
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<a name="US_IMR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> US_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>US2</b> <i><a href="AT91M55800A_h.html#AT91C_US2_IMR">AT91C_US2_IMR</a></i> 0xFFFC8010</font><font size="-2"><li><b>US1</b> <i><a href="AT91M55800A_h.html#AT91C_US1_IMR">AT91C_US1_IMR</a></i> 0xFFFC4010</font><font size="-2"><li><b>US0</b> <i><a href="AT91M55800A_h.html#AT91C_US0_IMR">AT91C_US0_IMR</a></i> 0xFFFC0010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
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<a name="US_CSR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> US_CSR  <i>Channel Status Register</i></h4><ul><null><font size="-2"><li><b>US2</b> <i><a href="AT91M55800A_h.html#AT91C_US2_CSR">AT91C_US2_CSR</a></i> 0xFFFC8014</font><font size="-2"><li><b>US1</b> <i><a href="AT91M55800A_h.html#AT91C_US1_CSR">AT91C_US1_CSR</a></i> 0xFFFC4014</font><font size="-2"><li><b>US0</b> <i><a href="AT91M55800A_h.html#AT91C_US0_CSR">AT91C_US0_CSR</a></i> 0xFFFC0014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="US_PARE"></a><b>US_PARE</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_PARE">AT91C_US_PARE</a></font></td><td><b>Parity Error Interrupt</b><br>1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last Reset Status Bits command.<br>0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_TIMEOUT"></a><b>US_TIMEOUT</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TIMEOUT">AT91C_US_TIMEOUT</a></font></td><td><b>Receiver Time-out</b><br>0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.<br>1 = There has been a time-out since the last Start Time-out command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="US_TXEMPTY"></a><b>US_TXEMPTY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TXEMPTY">AT91C_US_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.<br>1 = There are no characters in either US_THR or the Transmit Shift Register. TXEMPTY is 1 after Parity, Stop Bit and Time-guard have been transmitted. TXEMPTY is 1 after stop bit has been sent, or after Time-guard has been sent if US_TTGR is not 0.<br>Equal to zero when the debug unit is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one if the transmitter is disabled.</td></tr>
</null></table>
<a name="US_RHR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> US_RHR  <i>Receiver Holding Register</i></h4><ul><null><font size="-2"><li><b>US2</b> <i><a href="AT91M55800A_h.html#AT91C_US2_RHR">AT91C_US2_RHR</a></i> 0xFFFC8018</font><font size="-2"><li><b>US1</b> <i><a href="AT91M55800A_h.html#AT91C_US1_RHR">AT91C_US1_RHR</a></i> 0xFFFC4018</font><font size="-2"><li><b>US0</b> <i><a href="AT91M55800A_h.html#AT91C_US0_RHR">AT91C_US0_RHR</a></i> 0xFFFC0018</font></null></ul><br>Last character received if RXRDY is set. When number of data bits is less than 8 bits, the bits are right-aligned. All non-sig-nificant bits read zero.<a name="US_THR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> US_THR  <i>Transmitter Holding Register</i></h4><ul><null><font size="-2"><li><b>US2</b> <i><a href="AT91M55800A_h.html#AT91C_US2_THR">AT91C_US2_THR</a></i> 0xFFFC801C</font><font size="-2"><li><b>US1</b> <i><a href="AT91M55800A_h.html#AT91C_US1_THR">AT91C_US1_THR</a></i> 0xFFFC401C</font><font size="-2"><li><b>US0</b> <i><a href="AT91M55800A_h.html#AT91C_US0_THR">AT91C_US0_THR</a></i> 0xFFFC001C</font></null></ul><br>Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned.<a name="US_BRGR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> US_BRGR  <i>Baud Rate Generator Register</i></h4><ul><null><font size="-2"><li><b>US2</b> <i><a href="AT91M55800A_h.html#AT91C_US2_BRGR">AT91C_US2_BRGR</a></i> 0xFFFC8020</font><font size="-2"><li><b>US1</b> <i><a href="AT91M55800A_h.html#AT91C_US1_BRGR">AT91C_US1_BRGR</a></i> 0xFFFC4020</font><font size="-2"><li><b>US0</b> <i><a href="AT91M55800A_h.html#AT91C_US0_BRGR">AT91C_US0_BRGR</a></i> 0xFFFC0020</font></null></ul><br>Clock Divisor:<br>0 Disables Clock<br>1 Clock Divisor Bypass<br>2 to 65535 Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD)<br>Baud Rate (Synchronous Mode) = Selected Clock/CD<br>Notes: 1. In Synchronous Mode, when either external clock (clk_ext or fdiv1) is selected, the value programmed must be even to ensure a 50:50 mark:space ratio.<br>In Synchronous Mode, when the internal clock (clock) is selected, the CD can be even and the duty clock is 50:50.<br>2. Clock divisor bypass (CD = 1) must not be used when the internal clock (clock) is selected (USCLKS = 0).<br>3. In Asynchronous Mode, the divisor of Selected Clock depends upon the value of the bit, OVER in US_MR.<a name="US_RTOR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> US_RTOR  <i>Receiver Time-out Register</i></h4><ul><null><font size="-2"><li><b>US2</b> <i><a href="AT91M55800A_h.html#AT91C_US2_RTOR">AT91C_US2_RTOR</a></i> 0xFFFC8024</font><font size="-2"><li><b>US1</b> <i><a href="AT91M55800A_h.html#AT91C_US1_RTOR">AT91C_US1_RTOR</a></i> 0xFFFC4024</font><font size="-2"><li><b>US0</b> <i><a href="AT91M55800A_h.html#AT91C_US0_RTOR">AT91C_US0_RTOR</a></i> 0xFFFC0024</font></null></ul><br>Time-out Value:<br>0 Disables the RX Time-out function.<br>1-65535 The Time-out counter is loaded with TO (16 bits) when the Start Time-out command is given or when each new data character is received (after reception has started).<a name="US_TTGR"></a><h4><a href="#USART">USART</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> US_TTGR  <i>Transmitter Time-guard Register</i></h4><ul><null><font size="-2"><li><b>US2</b> <i><a href="AT91M55800A_h.html#AT91C_US2_TTGR">AT91C_US2_TTGR</a></i> 0xFFFC8028</font><font size="-2"><li><b>US1</b> <i><a href="AT91M55800A_h.html#AT91C_US1_TTGR">AT91C_US1_TTGR</a></i> 0xFFFC4028</font><font size="-2"><li><b>US0</b> <i><a href="AT91M55800A_h.html#AT91C_US0_TTGR">AT91C_US0_TTGR</a></i> 0xFFFC0028</font></null></ul><br>Time-guard duration = TG x Bit Period:<br>0 Disables the TX Time-out function.<br>1-255 TXD is inactive high after the transmission of each character for the time-guard duration.<a name="US_PDC"></a><h4><a href="#USART">USART</a>: <i><a href="AT91M55800A_h.html#AT91S_PDC">AT91S_PDC</a></i> US_PDC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>US2</b> <i><a href="#AT91C_US2_US">AT91C_US2_US</a></i> 0xFFFC8030</font><font size="-2"><li><b>US1</b> <i><a href="#AT91C_US1_US">AT91C_US1_US</a></i> 0xFFFC4030</font><font size="-2"><li><b>US0</b> <i><a href="#AT91C_US0_US">AT91C_US0_US</a></i> 0xFFFC0030</font></null></ul></null><hr></html>