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eb55评估板例程 for ads

<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_CLKS_FDIV1"></a><b>US_CLKS_FDIV1</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CLKS_FDIV1">AT91C_US_CLKS_FDIV1</a></font></td><td><br>fdiv1</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_CLKS_SLOW"></a><b>US_CLKS_SLOW</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CLKS_SLOW">AT91C_US_CLKS_SLOW</a></font></td><td><br>slow_clock (ARM)</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_CLKS_EXT"></a><b>US_CLKS_EXT</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CLKS_EXT">AT91C_US_CLKS_EXT</a></font></td><td><br>External (SCK)</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">7..6</td><td align="CENTER"><a name="US_CHRL"></a><b>US_CHRL</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_CHRL">AT91C_US_CHRL</a></font></td><td><b>Clock Selection (Baud Rate generator Input Clock</b><br>Start, stop and parity bits are added to the character length.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_CHRL_5_BITS"></a><b>US_CHRL_5_BITS</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CHRL_5_BITS">AT91C_US_CHRL_5_BITS</a></font></td><td><br>Character Length: 5 bits</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_CHRL_6_BITS"></a><b>US_CHRL_6_BITS</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CHRL_6_BITS">AT91C_US_CHRL_6_BITS</a></font></td><td><br>Character Length: 6 bits</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_CHRL_7_BITS"></a><b>US_CHRL_7_BITS</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CHRL_7_BITS">AT91C_US_CHRL_7_BITS</a></font></td><td><br>Character Length: 7 bits</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_CHRL_8_BITS"></a><b>US_CHRL_8_BITS</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CHRL_8_BITS">AT91C_US_CHRL_8_BITS</a></font></td><td><br>Character Length: 8 bits</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="US_SYNC"></a><b>US_SYNC</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_SYNC">AT91C_US_SYNC</a></font></td><td><b>Synchronous Mode Select</b><br>0 = USART operates in Asynchronous Mode.<br>1 = USART operates in Synchronous Mode</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..9</td><td align="CENTER"><a name="US_PAR"></a><b>US_PAR</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_PAR">AT91C_US_PAR</a></font></td><td><b>Parity type</b><br>When the PAR field is set to Even parity, the parity bit is set (&#147;1&#148;) if the data parity is Odd in order to ensure an even parity on the Data and Parity field.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_PAR_EVEN"></a><b>US_PAR_EVEN</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_PAR_EVEN">AT91C_US_PAR_EVEN</a></font></td><td><br>Even Parity</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_PAR_ODD"></a><b>US_PAR_ODD</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_PAR_ODD">AT91C_US_PAR_ODD</a></font></td><td><br>Odd Parity</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_PAR_SPACE"></a><b>US_PAR_SPACE</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_PAR_SPACE">AT91C_US_PAR_SPACE</a></font></td><td><br>Parity forced to 0 (Space)</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_PAR_MARK"></a><b>US_PAR_MARK</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_PAR_MARK">AT91C_US_PAR_MARK</a></font></td><td><br>Parity forced to 1 (Mark)</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="US_PAR_NONE"></a><b>US_PAR_NONE</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_PAR_NONE">AT91C_US_PAR_NONE</a></font></td><td><br>No Parity</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="US_PAR_MULTI_DROP"></a><b>US_PAR_MULTI_DROP</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_PAR_MULTI_DROP">AT91C_US_PAR_MULTI_DROP</a></font></td><td><br>Multi-drop mode</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">13..12</td><td align="CENTER"><a name="US_NBSTOP"></a><b>US_NBSTOP</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_NBSTOP">AT91C_US_NBSTOP</a></font></td><td><b>Number of Stop bits</b><br>The interpretation of the number of stop bits depends on SYNC.<br>1.5 or 2 stop bits are reserved for the TX function. The RX function uses only the 1 stop bit (there is no check on the 2 stop bit time slot if NBSTOP = 10).<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_NBSTOP_1_BIT"></a><b>US_NBSTOP_1_BIT</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_NBSTOP_1_BIT">AT91C_US_NBSTOP_1_BIT</a></font></td><td><br>1 stop bit</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_NBSTOP_15_BIT"></a><b>US_NBSTOP_15_BIT</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_NBSTOP_15_BIT">AT91C_US_NBSTOP_15_BIT</a></font></td><td><br>Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_NBSTOP_2_BIT"></a><b>US_NBSTOP_2_BIT</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_NBSTOP_2_BIT">AT91C_US_NBSTOP_2_BIT</a></font></td><td><br>2 stop bits</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="US_CHMODE"></a><b>US_CHMODE</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_CHMODE">AT91C_US_CHMODE</a></font></td><td><b>Channel Mode</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="US_CHMODE_NORMAL"></a><b>US_CHMODE_NORMAL</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CHMODE_NORMAL">AT91C_US_CHMODE_NORMAL</a></font></td><td><br>Normal Mode: The USART channel operates as an RX/TX USART.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="US_CHMODE_AUTO"></a><b>US_CHMODE_AUTO</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CHMODE_AUTO">AT91C_US_CHMODE_AUTO</a></font></td><td><br>Automatic Echo: Receiver Data Input is connected to the TXD pin.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="US_CHMODE_LOCAL"></a><b>US_CHMODE_LOCAL</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CHMODE_LOCAL">AT91C_US_CHMODE_LOCAL</a></font></td><td><br>Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="US_CHMODE_REMOTE"></a><b>US_CHMODE_REMOTE</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_US_CHMODE_REMOTE">AT91C_US_CHMODE_REMOTE</a></font></td><td><br>Remote Loopback: RXD pin is internally connected to TXD pin.</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="US_MODE9"></a><b>US_MODE9</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_MODE9">AT91C_US_MODE9</a></font></td><td><b>9-bit Character length</b><br>0 = CHRL defines character length.<br>1 = 9-bit character length.<br>MODE9 has priority on character length.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="US_CKLO"></a><b>US_CKLO</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_CKLO">AT91C_US_CKLO</a></font></td><td><b>Clock Output Select</b><br>0 = The USART does not drive the SCK pin.<br>1 = The USART drives the SCK pin if USCLKS[1] is 0.</td></tr>
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<a name="US_IER"></a><h4><a href="#USART">USART</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> US_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>US2</b> <i><a href="AT91M55800A_h.html#AT91C_US2_IER">AT91C_US2_IER</a></i> 0xFFFC8008</font><font size="-2"><li><b>US1</b> <i><a href="AT91M55800A_h.html#AT91C_US1_IER">AT91C_US1_IER</a></i> 0xFFFC4008</font><font size="-2"><li><b>US0</b> <i><a href="AT91M55800A_h.html#AT91C_US0_IER">AT91C_US0_IER</a></i> 0xFFFC0008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="US_RXRDY"></a><b>US_RXRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_RXRDY">AT91C_US_RXRDY</a></font></td><td><b>RXRDY Interrupt</b><br>0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.<br>1 = At least one complete character has been received and the US_RHR has not yet been read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="US_TXRDY"></a><b>US_TXRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_TXRDY">AT91C_US_TXRDY</a></font></td><td><b>TXRDY Interrupt</b><br>0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.<br>1 = There is no character in the US_THR.<br>Equal to zero when the USART3 is disabled or at reset. The Transmitter Enable command (in US_CR) sets this bit to 1 if the transmitter was previously disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="US_RXBRK"></a><b>US_RXBRK</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_RXBRK">AT91C_US_RXBRK</a></font></td><td><b>Break Received/End of Break</b><br>0 = No Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.<br>1 = Break Received or End of Break detected since the last Reset Status Bits command in the Control Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="US_ENDRX"></a><b>US_ENDRX</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_ENDRX">AT91C_US_ENDRX</a></font></td><td><b>End of Receive Transfer Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="US_ENDTX"></a><b>US_ENDTX</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_ENDTX">AT91C_US_ENDTX</a></font></td><td><b>End of Transmit Interrupt</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="US_OVRE"></a><b>US_OVRE</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_OVRE">AT91C_US_OVRE</a></font></td><td><b>Overrun Interrupt</b><br>0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.<br>1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last Reset Status Bits command.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="US_FRAME"></a><b>US_FRAME</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_US_FRAME">AT91C_US_FRAME</a></font></td><td><b>Framing Error Interrupt</b><br>0 = No stop bit has been detected low since the last Reset Status Bits command.<br>1 = At least one stop bit has been detected low since the last Reset Status Bits command.</td></tr>