at91fr.h

AT91FR40162的闪灯子程序

#ifndef  _AT91FR_
#define  _AT91FR_

typedef	unsigned char		BYTE;

#define	U8			unsigned char
#define	U16		unsigned short
#define	U32		unsigned int
#define	REG8		volatile unsigned char
#define	REG16		volatile unsigned short
#define	REG32		volatile unsigned int
#define	VPchar	*(REG8 *)
#define	VPshort	*(REG16 *)
#define	VPint		*(REG32 *)
#define	Pchar		(REG8 *)
#define	Pshort	(REG16 *)
#define	Pint		(REG32 *)

#define	FLASH_BASE      (0x01000000)

// EBI User Interface
#define	EBI_BASE		0xFFE00000
#define	EBI_CSR0		(VPint(EBI_BASE))				// Chip Select Register 0
#define	EBI_CSR1		(VPint(EBI_BASE+0x04))		// Chip Select Register 1
#define	EBI_CSR2		(VPint(EBI_BASE+0x08))		// Chip Select Register 2
#define	EBI_CSR3		(VPint(EBI_BASE+0x0C))		// Chip Select Register 3
#define	EBI_CSR4		(VPint(EBI_BASE+0x10))		// Chip Select Register 4
#define	EBI_CSR5		(VPint(EBI_BASE+0x14))		// Chip Select Register 5
#define	EBI_CSR6		(VPint(EBI_BASE+0x18))		// Chip Select Register 6
#define	EBI_CSR7		(VPint(EBI_BASE+0x1C))		// Chip Select Register 7
#define	EBI_RCR		(VPint(EBI_BASE+0x20))		// Remap Control Register
#define	EBI_MCR		(VPint(EBI_BASE+0x24))		// Memory Control Register

// Parallel IO Interface
#define	PIO_BASE		0xFFFF0000
#define	PIO_PER		(VPint(PIO_BASE))				// PIO Enable Register
#define	PIO_PDR		(VPint(PIO_BASE+0x04))		// PIO Disable Register
#define	PIO_PSR		(VPint(PIO_BASE+0x08))		// PIO Status Register
#define	PIO_OER		(VPint(PIO_BASE+0x10))		// PIO Output Enable Register
#define	PIO_ODR		(VPint(PIO_BASE+0x14))		// PIO Output Disable Register
#define	PIO_OSR		(VPint(PIO_BASE+0x18))		// PIO Output Status Register
#define	PIO_SODR		(VPint(PIO_BASE+0x30))		// PIO Set Output Data Register
#define	PIO_CODR		(VPint(PIO_BASE+0x34))		// PIO Clear Output Data Register
#define	PIO_ODSR		(VPint(PIO_BASE+0x38))		// PIO Output Data StatusRegister
#define	PIO_PDSR		(VPint(PIO_BASE+0x3C))		// PIO Pin Data Status Register

// USART 0 Interface
#define	US0_BASE		0xFFFD0000
#define	US0_CR		(VPint(US0_BASE))				// US0 Control Register(w)
#define	US0_MR		(VPint(US0_BASE+0x04))		// US0 Mode Register(rw)(0)
#define	US0_IER		(VPint(US0_BASE+0x08))		// US0 Interrupt Enable Register(w)
#define	US0_IDR		(VPint(US0_BASE+0x0C))		// US0 Interrupt Disable Register(w)
#define	US0_IMR		(VPint(US0_BASE+0x10))		// US0 Interrupt Mask Register(r)(0)
#define	US0_CSR		(VPint(US0_BASE+0x14))		// US0 Channel Status Register(r)(0x18)
#define	US0_RHR		(VPint(US0_BASE+0x18))		// US0 Receiver Holding Register(r)(0)
#define	US0_THR		(VPint(US0_BASE+0x1C))		// US0 Transmitter Holding Register(w)
#define	US0_BRGR		(VPint(US0_BASE+0x20))		// US0 Baud Rate Generator Register(rw)(0)
#define	US0_RTOR		(VPint(US0_BASE+0x24))		// US0 Receiver Time-out Register(rw)(0)
#define	US0_TTGR		(VPint(US0_BASE+0x28))		// US0 Transmitter Time-guard Register(rw)(0)
#define	US0_RPR		(VPint(US0_BASE+0x30))		// US0 Receive Pointer Register(rw)(0)
#define	US0_RCR		(VPint(US0_BASE+0x34))		// US0 Receive Counter Register(rw)(0)
#define	US0_TPR		(VPint(US0_BASE+0x38))		// US0 Transmit Pointer Register(rw)(0)
#define	US0_TCR		(VPint(US0_BASE+0x3C))		// US0 Transmit Counter Register(rw)(0)

// USART 1 Interface
#define	US1_BASE		0xFFFCC000
#define	US1_CR		(VPint(US1_BASE))				// US1 Control Register(w)
#define	US1_MR		(VPint(US1_BASE+0x04))		// US1 Mode Register(rw)(0)
#define	US1_IER		(VPint(US1_BASE+0x08))		// US1 Interrupt Enable Register(w)
#define	US1_IDR		(VPint(US1_BASE+0x0C))		// US1 Interrupt Disable Register(w)
#define	US1_IMR		(VPint(US1_BASE+0x10))		// US1 Interrupt Mask Register(r)(0)
#define	US1_CSR		(VPint(US1_BASE+0x14))		// US1 Channel Status Register(r)(0x18)
#define	US1_RHR		(VPint(US1_BASE+0x18))		// US1 Receiver Holding Register(r)(0)
#define	US1_THR		(VPint(US1_BASE+0x1C))		// US1 Transmitter Holding Register(w)
#define	US1_BRGR		(VPint(US1_BASE+0x20))		// US1 Baud Rate Generator Register(rw)(0)
#define	US1_RTOR		(VPint(US1_BASE+0x24))		// US1 Receiver Time-out Register(rw)(0)
#define	US1_TTGR		(VPint(US1_BASE+0x28))		// US1 Transmitter Time-guard Register(rw)(0)
#define	US1_RPR		(VPint(US1_BASE+0x30))		// US1 Receive Pointer Register(rw)(0)
#define	US1_RCR		(VPint(US1_BASE+0x34))		// US1 Receive Counter Register(rw)(0)
#define	US1_TPR		(VPint(US1_BASE+0x38))		// US1 Transmit Pointer Register(rw)(0)
#define	US1_TCR		(VPint(US1_BASE+0x3C))		// US1 Transmit Counter Register(rw)(0)

#define	PIOTXD0				(1<<14)
#define	PIORXD0				(1<<15)
#define	US_TXDIS				(1<<7)
#define	US_RXDIS				(1<<5)
#define	US_RSTTX				(1<<3)
#define	US_RSTRX				(1<<2)
#define	US_RXEN				(1<<4)
#define	US_TXEN				(1<<6)
/*
#define	BAUD_115200			36
#define	BAUD_19200			217
#define	BAUD_9600			434
*/
#define	PS_BASE		0xFFFF4000						// Power saving
#define	PS_CR			(VPint(PS_BASE))				// PS Control Register(w)
#define	PS_PCER		(VPint(PS_BASE+0x04))		// PS Peripheral Clock Enable Register(w)
#define	PS_PCDR		(VPint(PS_BASE+0x08))		// PS Peripheral Clock Disable Register(w)
#define	PS_PCSR		(VPint(PS_BASE+0x0C))		// PS Peripheral Clock Status Register(r)

// Advanced Interrupt Controller
#define	AIC_BASE		0xFFFFF000
#define	AIC_IDCR		(VPint(AIC_BASE+0x124))		// AIC Disable Register

#define EBI_CSR_0       ((unsigned int )(FLASH_BASE | 0x2539))     // 0x01000000, 16MB, 2 tdf, 16 bits, 7 WS

#endif