📄 pcic_t.tdf
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-- lt_low_ack_OR : NODE; -- Local Target Low Acknowledge Output Register
-- lt_hi_ack_R : DFFE; -- Local Target High Acknowledge Signal
-- lt_hi_ack_OR : NODE; -- Local Target High Acknowledge Output Register
data_timeout_error : NODE; -- Indicates a data timeout error
lt_rdynR : DFFE; -- Register version of local target ready
lt_rdynR_R : DFFE;
targ_access : NODE;
EXP_ROM_HIT : NODE;
trg_OR_advance : DFFE;
lt_ldata_ack : NODE; -- Target local output Data Acknowledge -- Low
lt_ldata_ack_lc1 : NODE;
lt_lack : TFFE; -- Local Target toggle flop to determine where the data is valid
lt_lack_lc1 : NODE;
lt_hdata_ack : NODE; -- Target local output Data Acknowledge -- High
lt_hdata_ack_R : DFFE;
lt_ldata_ack_R : DFFE;
-- lt_ldata_ack_RR : DFFE;
64_trans : pcic_sr; -- 64 bit transaction indicator
64_trans_rst_lc1 : NODE;
64_trans_rst_lc2 : NODE;
64_trans_set : NODE;
fast_back : pcic_sr;
direct_xfr : LCELL;--node; -- Target Read State Machine path
burst_trans : pcic_sr; -- Burst Transaction
dati_hr_ena_lc : NODE;
dac_cfg : NODE; -- To check during configuration time whether system placed target in the 32 memory space although
-- requested 64-bit memory space (for 2Gbytes and less memory size)
hi_low_sel_lc1 : NODE;
hi_low_sel_lc2 : NODE;
hi_low_sel_d1 : DFFE;
hi_low_sel_d1_lc1 : NODE;
hi_low_sel_d1_lc1a : NODE;
hi_low_sel_d1_lc2 : NODE;
hi_low_sel_d1_lc3 : NODE;
hi_low_sel_d1_lc4 : NODE;
hi_low_sel_d1_lc5 : NODE;
hi_low_sel_d1_lc5a : NODE;
hi_low_sel_d1_lc6 : NODE;
hi_low_sel_d2 : DFFE;
hi_low_sel_d2_lc1 : NODE;
hi_low_sel_d2_lc2 : NODE;
hi_low_sel_d2_lc3 : NODE;
hi_low_sel_d2_lc4 : NODE;
hi_low_sel_d2_lc5 : NODE;
hi_low_sel_d2_lc6 : NODE;
hi_low_sel_d3 : DFFE;
hi_low_sel_d3_lc1 : NODE;
hi_low_sel_d3_lc2 : NODE;
WAIT_wait32 : DFFE;
ador_hi_dena_lc : NODE;
BEGIN
junk = junk or io_bar_hit or mstr_actv or lr_wait_32_d or mem_cyc or lw_idle_d or pxfr
or lr_idle_d or lr_wait_d or lr_pxfr_d or LR_PXFR_32_d OR mstr_dac_decode
or cap_ptr_ena_lc1 or cap_ptr_ena_lc2;
-- Frame Input Register
frame_IR.clk = clk;
frame_IR.clrn = rstn;
frame_IR.d = frame;
-- IRDYN Input Register
irdyRn.clk = clk;
irdyRn.clrn = rstn;
irdyRn.d = not irdy;
-- Frame Delayed Two Clocks
frame_I1R.clk = clk;
frame_I1R.clrn = rstn;
frame_I1R.d = frame_IR;
frame_I2R.clk = clk;
frame_I2R.clrn = rstn;
frame_I2R.d = frame_I1R;
-- idsel Input Register
idsel_IR.clk = clk;
idsel_IR.clrn = rstn;
idsel_IR.d = idsel;
dac_sr.clk = clk;
dac_sr.clrn = rstn;
dac_sr.prn = VCC;
dac_sr.s = adr_phase and (cben_ir_address[3..0]==B"1101");--(cben_ir_address[3] and cben_ir_address[2] and not cben_ir_address[1] and cben_ir_address[0]);
dac_sr.r = TS_IDLE and not adr_phase;
dac_cfg = dac_sr.q;
dac_sr_out = dac_cfg;
adr_phase_lc1 = ((frame_IR and NOT frame_I1R% and not (cben_ir_address[3..0] == B"1101")%) OR (frame_I1R and NOT frame_I2R and dac_sr.q));
adr_phase = adr_phase_lc1 and not mstr_actv ;
adr_phase_out = adr_phase;
-- **********************************************************************
-- **** Instantiate the config.tdf ****
-- **********************************************************************
cfg.clk = clk; -- PCI Clock
cfg.rstn = rstn; -- PCI Reset
cfg.cben_IR[3..0] = cben_ir_data[3..0];--cben_IR_address[3..0]; -- Registered cben signals
cfg.cben_IR_addr[3..0] = cben_IR_address[3..0]; -- Registered cben signals
cfg.ad_IR[31..0] = ad_ir_data[31..0];--ad_ir_address[31..0]; -- Registered PCI Address/Data Bus
cfg.ad_ir_addr[31..0] = ad_ir_address[31..0];
cfg.adr_phase = adr_phase; -- High One Clock after Address Phase
cfg.cfg_dat_vld = cfg_dat_vld; -- Configuration Data is valid at ad_IR[31..0]
cfg.serr_det = serr_sig_set; -- Signaled SERR
cfg.adr_dec_ena = cfg_adr_dec_ena; -- Enable Configuration Address Decoder
cfg.tabrt_set = tabrt_set; -- Signaled Target Abort
cfg.tabrt_rcvd_set = tabrt_rcvd_set; -- Recieved Target Abort
cfg.mabrt_set = mstr_abrt_set; -- Recieved Master Abort
cfg.bar_hit_rst = bar_hit_rst; -- Reset the bar Hit bit at end of PCI access
cfg.perr_det_set = perr_det_set; -- Detected Parity Error
cfg.perr_rep_set = perr_rep_set; -- Data Parity Error Signaled
cfg.dac_cfg = dac_cfg;
mem_bar_hit = cfg.mem_bar_hit; -- One of the Memory BARs has Positive Address Compare
io_bar_hit = cfg.io_bar_hit; -- One of the I/O BARs has Positive Address Compare
cfg_dat_out[31..0] = cfg.cfg_dat_out[31..0];-- Configuration Data Output
-- Command Register Outputs
io_ena = cfg.io_ena; -- I/O Space Enable
mem_ena = cfg.mem_ena; -- Memory Space Enable
mstr_ena = cfg.mstr_ena; -- Bus Master Enable
mwi_ena = cfg.mwi_ena; -- Memory Write and Invalidate Enable
perr_ena = cfg.perr_ena; -- Pariy Error Response Enable
serr_ena = cfg.serr_ena; -- SERR Enable
-- dac_cfg = cfg.dac_out;
-- Status Register Outputs
cfg_perr_rep = cfg.perr_rep; -- Data Parity Error Signaled
cfg_tabrt_sig = cfg.tabrt_sig; -- Signaled Target Abort
cfg_tabrt_rcvd = cfg.tabrt_rcvd; -- Recieved Target Abort
cfg_mabrt_rcvd = cfg.mabrt_rcvd; -- Recieved Master Abort
cfg_serr_sig = cfg.serr_sig; -- Signaled SERR
cfg_perr_det = cfg.perr_det; -- Detected Parity Error
lat_dat[7..0] = cfg.lat_dat[7..0]; -- Latency Timer Register Data
cache_dat[7..0] = cfg.cache_dat[7..0]; -- Cache Line Register Data
base_hit[5..0] = cfg.base_hit[5..0]; -- Base Address Register Comparison Outputs
-- Local Side Configuration Space Support
cfg.lcfg_adr[7..0] = lcfg_adr[7..0]; -- Local Configuration Address
cfg.lcfg_ben[3..0] = lcfg_ben[3..0]; -- Local Configuration Byte enables
cfg.lcfg_dat_in[31..0] = lcfg_dat_in[31..0]; -- Local Configuration Data Input Bus
cfg.lcfg_adr_vld = lcfg_adr_vld; -- Local Configuration Address Valid
cfg.lcfg_dat_vld = lcfg_dat_vld; -- Local Configuration data Valid
lcfg_dat_out[31..0] = cfg.lcfg_dat_out[31..0];-- Local Configuration Data Output
-- **********************************************************************
-- **** END Instatiate of Config.tdf ****
-- **********************************************************************
-- Configuration Status Register error conditions
tabrt_sig_cyc.clk = clk;
tabrt_sig_cyc.clrn = rstn;
tabrt_sig_cyc.prn = VCC;
tabrt_sig_cyc.s = tabrt_set;
tabrt_sig_cyc.r = TS_ADR_VLD;
tabrt_set = not lt_abortn; -- Signaled Target Abort
tabrt_rcvd_set = targ_abrt_set; -- Recieved Target Abort
-- Target Control State Machine
IF (OPTIMIZE_TARG == "NO") GENERATE
Assert REPORT "NOT OPTIMIZING TARGET"
Severity Warning;
targ_sm.clk = clk;
targ_sm.reset = !rstn;
CASE targ_sm IS
WHEN TS_IDLE => IF targ_trig then -- Address Hit one Of BARs
targ_sm = TS_ADR_VLD ;
ELSE
targ_sm = TS_IDLE;
END IF;
-- Address Valid State, Turn on Otput Drivers
WHEN TS_ADR_VLD => IF serr_sig_set then -- Address Parity Error Detected
targ_sm = TS_IDLE;
-- ELSIF (not lt_abortn and not cfg_cyc) THEN -- Abort Signaled -- Devsel must be asserted at least one clock cycle
-- targ_sm = TS_DISC;
ELSE
targ_sm = TS_ADR_CLMD; -- Goto Address Claimed State
END IF;
WHEN TS_ADR_CLMD => -- If retry, Disconnect, Abort is signaled in I/O or Mem Cycle
IF (((retry or not lt_discn or not lt_abortn) and not cfg_cyc) or mstr_actv) THEN
targ_sm = TS_DISC;
ELSIF ((not lt_rdyn) or cfg_cyc) THEN -- Memory Write Cycle
targ_sm = TS_DXFR;
ELSE
targ_sm = TS_ADR_CLMD;
END IF;
-- Transfer Data state
WHEN TS_DXFR => IF (not lt_abortn or not lt_discn) Then -- Disconnect or Abort Signaled
targ_sm = TS_DISC;
ELSIF ( (not frame and trdy_OR) ) THEN-- Normal Master Termination Detected
targ_sm = TS_TURN_AR;
ELSE
targ_sm = TS_DXFR;
END IF;
-- Wait for Data to be recieved from Local Side during a read
WHEN TS_LRD_WAIT => IF (not lt_abortn OR not lt_discn) THEN -- Abort or Retry is signaled from Local Side
targ_sm = TS_DISC;
ELSIF (LR_PXFR) THEN -- One Word is recieved from Local Side during Mem Cycle
targ_sm = TS_DXFR;
ELSE
targ_sm = TS_LRD_WAIT; -- No Words Have been recieved and termination is not signaled
END IF;
-- Disconnect State, Retry, Abort, Disconnect
WHEN TS_DISC => IF (not frame) Then -- Master Terminated transactions
targ_sm = TS_TURN_AR;
ELSE
targ_sm = TS_DISC; -- Master Did not terminate transaction
END IF;
-- Turn around State
WHEN TS_TURN_AR => targ_sm = TS_IDLE;
END CASE ;
%
TS_IDLE = not TS_IDLE_not;
TS_IDLE_d = (TS_IDLE and not targ_trig)
OR (TS_ADR_VLD and serr_sig_set)
OR (TS_TURN_AR);
TS_ADR_VLD_d = (TS_IDLE and targ_trig);
TS_ADR_CLMD_d = (TS_ADR_VLD and not serr_sig_set)
OR (TS_ADR_CLMD and not ((retry or not lt_discn or not lt_abortn) and not cfg_cyc) and not ((not lt_rdyn) or cfg_cyc));
TS_DXFR_d = (TS_ADR_CLMD and not ((retry or not lt_discn or not lt_abortn) and not cfg_cyc) and ((not lt_rdyn) or cfg_cyc))
OR (TS_DXFR and not (not lt_abortn or not lt_discn) and not (not frame and trdy_OR))
OR (TS_LRD_WAIT and not (not lt_abortn OR not lt_discn) and LR_PXFR);
TS_LRD_WAIT_d = (TS_LRD_WAIT and not (not lt_abortn OR not lt_discn) and not LR_PXFR);
TS_DISC_d = (TS_ADR_CLMD and ((retry or not lt_discn or not lt_abortn) and not cfg_cyc))
OR (TS_DXFR and (not lt_abortn or not lt_discn))
OR (TS_LRD_WAIT and (not lt_abortn OR not lt_discn))
OR (TS_DISC and not (not frame));
TS_TURN_AR_d = (TS_DXFR and not (not lt_abortn or not lt_discn) and (not frame and trdy_OR))
OR (TS_DISC and (not frame));
%
lw_sm.clk = clk;
lw_sm.reset = NOT rstn;
---********
CASE lw_sm IS
WHEN LW_IDLE => IF (TS_ADR_CLMD and not lt_rdyn and not cfg_cyc and wr_rdn and not serr_sig_set and lt_abortn and not retry) THEN -- Only triggered in I/O or Mem Cycles and retry is not signaled
lw_sm = LW_LXFR;
LW_LXFR_d = VCC;
ELSE
lw_sm = LW_IDLE;
LW_IDLE_d = VCC;
END IF;
% Oliver Tan 1-11-99
-- Pipe Has no data
WHEN LW_LXFR => IF (not TS_DXFR) THEN -- Pipe is empty and targ_sm is finished
lw_sm = LW_DONE;
LW_DONE_d = VCC;
ELSIF (lt_rdyn and TS_DXFR and lt_ack_or) THEN -- pipe is full and local is waiting
lw_sm = LW_WAIT;
LW_WAIT_d = VCC;
ELSE
lw_sm = LW_LXFR; -- data is being transferred through pipe
LW_LXFR_d = VCC;
END IF;
-- Pipe Has Data But Local Side is asserting Wait
WHEN LW_WAIT => IF (data_timeout_error) THEN -- PCI has completed the transaction
lw_sm = LW_DONE; -- but local side asserted wait for
LW_DONE_d = VCC; -- too long
ELSIF ((not lt_rdyn and TS_DXFR) or TS_TURN_AR) THEN
lw_sm = LW_LXFR; -- Local is still asserting wait
LW_LXFR_d = VCC;
ELSE
lw_sm = LW_WAIT; -- Pipe is not empty and local xferring data
LW_WAIT_d = VCC;
END IF;
%
-- Pipe Has no data
WHEN LW_LXFR => --jot IF (not lt_rdyn and not TS_DXFR) THEN -- Pipe is empty and targ_sm is finished
IF (not lt_rdyn %and not TS_DXFR% and TS_DISC and irdy) THEN -- Pipe is empty and targ_sm is finished
lw_sm = LW_DONE; -- tmbw64_disc_2f.scf
LW_DONE_d = VCC;
ELSIF (TS_TURN_AR) THEN -- Pipe is empty and targ_sm is finished
lw_sm = LW_DONE; -- tmbw32_64_1pw_1a.scf
LW_DONE_d = VCC;
-- ELSIF (lt_rdyn and (%lt_ack_OR and% %lt_low_ack_OR or lt_hi_ack_OR or% irdy)) THEN -- Ored lt_ack_or and irdy to account for wait state on first data phase -- pipe is full and local is waiting
ELSIF (lt_rdyn and irdy and not TS_DISC) THEN -- Ored lt_ack_or and irdy to account for wait state on first data phase -- pipe is full and local is waiting
lw_sm = LW_WAIT;
LW_WAIT_d = VCC;
ELSE
lw_sm = LW_LXFR; -- data is being transferred through pipe
LW_LXFR_d = VCC;
END IF;
-- Pipe Has Data But Local Side is asserting Wait
WHEN LW_WAIT => IF (data_timeout_error) THEN -- PCI has completed the transaction
lw_sm = LW_DONE; -- but local side asserted wait for
LW_DONE_d = VCC; -- too long
ELSIF (lt_rdyn) THEN
lw_sm = LW_WAIT; -- Local is still asserting wait
LW_WAIT_d = VCC;
ELSIF (not lt_rdyn AND not TS_DXFR) THEN -- Pipe is empty and no more data
lw_sm = LW_DONE;
LW_DONE_d = VCC;
ELSE
lw_sm = LW_LXFR; -- Pipe is not empty and local xferring data
LW_LXFR_d = VCC;
END IF;
-- Pipe is empty and Local Side recieve all Data and PCI completed Transaction
WHEN LW_DONE => lw_sm = LW_IDLE;
LW_IDLE_d = VCC;
END CASE;
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