📄 pcic_t.tdf
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devsel_OR_lc5 : NODE;
ack64_OR : DFFE; -- Acknowledge 64 bit transactions
ack64_OR_lc1 : NODE;
ack64_OR_lc2 : NODE;
ack64_OR_lc3 : NODE;
ack64_OR_lc4 : NODE;
ack64_OR_lc5 : NODE;
64_trans_or : NODE;
stop_OR : NODE; -- PCI Stop Output
stop_R : NODE;
stop_or_not : DFFE;
frame_IR : DFFE; -- Active High FRAMEn Input Register
frame_I1R : DFFE; -- Active High FRAMEn Delayed Two Clocks
frame_I2R : DFFE; -- Active High FRAMEn Delayed Two Clocks
dac_sr : pcic_sr;
hi_adr_hr[31..0] : DFFE;
req64_R : DFFE;
irdyrn : DFFE; -- This is a registered version of PCI irdyn signal
idsel_IR : DFFE; -- IDSEL Input Register
perr_vldR : DFFE;
adr_phase_lc1 : LCELL; -- Address Phase Indicator delayed one clock
adr_phase : NODE;--LCELL; -- Address Phase Indicator delayed one clock
cfg : pcic_c; -- Instantiate Configuration Registers
mem_bar_hit : LCELL;--NODE; -- One of Memory BARs has a hit
io_bar_hit : NODE; -- One of I/O bars has a hit
tabrt_set : NODE; -- Status Register Target Abort Signaled Set
tabrt_rcvd_set : NODE; -- Status Register Target Abort Recieved Set
tabrt_sig_cyc : pcic_sr;
-- mabrt_set : NODE; -- Status Register Maser Abort Set
targ_trig : NODE; -- Target Access Triggered
targ_trig_lc1 : NODE;
targ_trig_lc2 : NODE;
junk : node;
ad_ir_ce_A_1 : NODE;
ad_ir_ce_A_2 : NODE;
-- ad_ir_ce_A_3 : NODE;
ad_ir_ce_A_4 : NODE;
ad_ir_ce_D_1 : NODE;
cben_ir_ce_A_1 : NODE;
cben_ir_ce_A_2 : NODE;
-- cben_ir_ce_A_3 : NODE;
cben_ir_ce_A_4 : NODE;
cben_ir_ce_D_1 : NODE;
-- cap_ptr_dat_R[7..0] : DFFE;
IF (OPTIMIZE_TARG == "NO") GENERATE
targ_sm : MACHINE of bits ( targ_smb[6..0]) WITH
STATES( TS_IDLE = B"0000000",
TS_ADR_VLD = B"0000011",
TS_ADR_CLMD = B"0000101",
TS_DXFR = B"0001001",
TS_LRD_WAIT = B"0010001",
TS_DISC = B"0100001",
TS_TURN_AR = B"1000001");
lw_sm : MACHINE OF BITS ( lw_smb[3..0]) WITH
STATES( LW_IDLE = B"0000",
LW_LXFR = B"0011",
LW_WAIT = B"0101",
LW_DONE = B"1001");
lr_sm : MACHINE OF BITS ( lr_smb[6..0]) WITH
STATES( LR_IDLE = B"0000000",
LR_PXFR = B"0000011",
LR_LXFR = B"0000101",
LR_WAIT = B"0001001",
LR_DONE = B"0010001",
LR_PXFR_32 = B"0100001",
LR_WAIT_32 = B"1000001");
-- Target Write Next State Nodes
LW_IDLE_d : NODE;
LW_LXFR_d : NODE;
LW_WAIT_d : NODE;
LW_DONE_d : NODE;
-- Target Read Next State Nodes
LR_IDLE_d : NODE;
LR_PXFR_d : NODE;
LR_LXFR_d : NODE;
LR_WAIT_d : NODE;
LR_DONE_d : NODE;
LR_PXFR_32_d : NODE;
LR_WAIT_32_d : NODE;
ELSE GENERATE
-- Target State Machine
TS_IDLE_not,
TS_ADR_VLD,
TS_ADR_CLMD,
TS_DXFR,
TS_LRD_WAIT,
TS_DISC,
TS_TURN_AR : DFFE;
TS_IDLE,
TS_IDLE_d,
TS_ADR_VLD_d,
TS_ADR_CLMD_d,
TS_DXFR_d,
TS_LRD_WAIT_d,
TS_DISC_d,
TS_TURN_AR_d : NODE;
TS_IDLE_d_lc : NODE;
TS_DXFR_d_lc1 : NODE;
TS_DXFR_d_lc2 : NODE;
TS_DXFR_d_lc3 : NODE;
TS_DXFR_d_lc4 : NODE;
TS_DXFR_d_lc5 : NODE;
-- Target Write State Machine
LW_IDLE_not,
LW_LXFR,
LW_WAIT,
LW_DONE : DFFE;
LW_IDLE,
LW_IDLE_d,
LW_LXFR_d,
LW_WAIT_d,
LW_DONE_d : NODE;
-- Target Read State Machine
LR_IDLE_not,
-- LR_PXFR,
LR_LXFR,
LR_WAIT,
LR_DONE,
-- LR_PXFR_32,
LR_WAIT_32 : DFFE;
LR_IDLE,
LR_IDLE_d,
-- LR_PXFR_d,
LR_LXFR_d,
LR_WAIT_d,
LR_DONE_d,
-- LR_PXFR_32_d,
LR_WAIT_32_d : NODE;
LR_PXFR_32_r1 : DFFE;
LR_PXFR_32_r2 : DFFE;
LR_PXFR_32 : NODE;
LR_PXFR_32_r1_d : NODE;
LR_PXFR_32_r2_d : NODE;
LR_PXFR_32_d : NODE;
LR_PXFR_32_hi_low_sel_lc1 : NODE;
LR_PXFR_32_hi_low_sel_lc2 : NODE;
-- LR_PXFR_32_r1_lc1 : NODE;
LR_PXFR_r1 : DFFE;
LR_PXFR_r2 : DFFE;
LR_PXFR : NODE;
LR_PXFR_r1_d : NODE;
LR_PXFR_r2_d : NODE;
LR_PXFR_d : NODE;
LR_WAIT_lc1 : NODE;
LR_WAIT_lc2 : NODE;
LR_WAIT_32_lc1 : NODE;
LR_WAIT_32_lc2 : NODE;
LR_PXFR_r1_d_lc1 : NODE;
LR_PXFR_r1_d_lc2 : NODE;
LR_PXFR_r1_d_lc3 : NODE;
LR_PXFR_r2_d_lc1 : NODE;
LR_PXFR_r2_d_lc2 : NODE;
LR_PXFR_32_r1_d_lc1 : NODE;
LR_PXFR_32_r1_d_lc2 : NODE;
LR_PXFR_32_r1_d_lc3 : NODE;
LR_PXFR_32_r2_d_lc1 : NODE;
LR_LXFR_d_lc1 : NODE;
LR_LXFR_d_lc2 : NODE;
LR_LXFR_d_lc3 : NODE;
LR_LXFR_d_lc4 : NODE;
LR_LXFR_d_lc5 : NODE;
LR_LXFR_d_lc6 : NODE;
END GENERATE;
retry : SRFF; -- Retry Indicator
retry_set : NODE;
retry_rst_lc1 : NODE;
retry_rst_lc2 : NODE;
lt_discnR : DFFE; -- Registered version of lt_discn wr_rdn : NODE; -- Data Cycle type
wr_rdn_FF : pcic_sr; -- Data Cycle type mem_cyc : SRFF; -- Memory Cycle Indicator
wr_rdn : NODE;
mem_cyc : SRFF;
cfg_cyc : SRFF; -- Configuration Cycle Indicator
io_cyc : SRFF; -- I/O Cycle Indicator
cfg_dat_vld : NODE;
cfg_adr_dec_ena : NODE; -- Enable Configuration Address Decoder
cfg_adr_dec_ena_lc1 : NODE; -- Enable Configuration Address Decoder
cfg_adr_dec_ena_lc2 : NODE; -- Enable Configuration Address Decoder
lreg_busy : SRFF; -- Local Side did not finish emptying the Write Pipeline
-- lt_frame_OR : SRFF; -- Local Targer Frame Output Register
-- lt_frame_or_rst : NODE;
-- lt_frame_or_set : NODE;
lt_frame_OR : SRFF; -- Local Targer Frame Output Register
lt_frame_or_rst : NODE;
lt_frame_or_rst_lc1 :NODE;
lt_frame_or_rst_lc2 :NODE;
lt_frame_or_rst_lc3 :NODE;
lt_frame_or_rst_lc4 :NODE;
lt_frame_or_set : NODE;
cap_ptr_ena : NODE;
cap_ptr_ena_lc1 : NODE;
cap_ptr_ena_lc2 : NODE;
cap_ptr_ena_sr : SRFF;
adoe : DFFE;
TURN_AR_R : DFFE;
--jot lt_rdy_IR : DFFE; -- lt_rdy Active High Input Register
pxfr : DFFE; -- This indicates that a PCI transferr has just occurred, Rising
-- edge when trdyn and irdyn are low will result in this going high
bar_hit_rst : NODE; -- This will reset the BAR_HIT after the current cycle is complete
rd_backoff : NODE; -- Indicates that Read Cycle should be stopped.
-- stop_lc[2..1] : NODE;
-- trdy_lc[7..2] : NODE;
-- trdy_lc1 : NODE;
trdy_lc[5..1] : LCELL;
trdy_lc1_1a : NODE;
trdy_lc1_1b : NODE;
trdy_lc1_1c : NODE;
trdy_lc1_1d : NODE;
trdy_lc1_1e : NODE;
trdy_lc1_2e : NODE;
trdy_lc1_1f : NODE;
trdy_lc1_1g : NODE;
trdy_lc1_1h : NODE;
trdy_lc1_1i : NODE;
trdy_lc1_1j : NODE;
trdy_lc1_1k : NODE;
trdy_lc1_1m : NODE;
trdy_hi_low_lc1 : NODE;
trdy_hi_low_lc2 : NODE;
trdy_lc3_1a : NODE;
trdy_lc3_1b : NODE;
trdy_lc4_1a : NODE;
trdy_lc5_1a : NODE;
trdy_lc5_1b : NODE;
trdy_lc5_1c : NODE;
-- stop_lc[3..1] : LCELL;
stop_lc[3..1] : LCELL;
stop_lc1_1a : LCELL;
stop_lc1_1b : LCELL;
stop_lc1_1c : LCELL;
stop_lc1_1d : LCELL;
stop_lc1_1e : LCELL;
stop_lc2_1a : LCELL;
stop_lc2_1b : LCELL;
stop_lc2_1c : LCELL;
stop_lc2_1d : LCELL;
stop_lc2_1e : LCELL;
stop_lc3_1a : LCELL;
stop_lc3_1b : LCELL;
lt_ack_R_r1 : DFFE; -- Local Target Acknowledge Register 1 Signal
lt_ack_R_r1_lc1 : NODE;
lt_ack_R_r1_lc2 : NODE;
lt_ack_R_r1_lc3 : NODE;
lt_ack_R_r1_lc4 : NODE;
lt_ack_R_r1_lc5 : NODE;
lt_ack_R_r1_lc6 : NODE;
lt_ack_R_r1_lc7 : NODE;
lt_ack_R_r1_lc8 : NODE;
lt_ack_R_r1_lc9 : NODE;
lt_ack_R_r1_lc10 : NODE;
lt_ack_R_r1_lc11 : NODE;
lt_ack_R_r2 : DFFE; -- Local Target Acknowledge Register 2 Signal
lt_ack_R_r2_lc1 : NODE;
lt_ack_R_r2_lc2 : NODE;
lt_ack_R_r2_lc3 : NODE;
lt_ack_R_r2_lc4 : NODE;
lt_ack_R_r2_lc5 : NODE;
lt_ack_R_r2_lc6 : NODE;
lt_ack_R_r2_lc7 : NODE;
lt_ack_R_r3 : DFFE; -- Local Target Acknowledge Register 2 Signal
lt_ack_R_r3_lc1 : NODE;
lt_ack_R_r3_lc2 : NODE;
lt_ack_R_r3_lc2a : NODE;
lt_ack_R_r3_lc2b : NODE;
lt_ack_R_r3_lc3 : NODE;
lt_ack_R_r3_lc4 : NODE;
lt_ack_R_r3_lc5 : NODE;
lt_ack_R : NODE; -- Local Target Acknowledge Signal
lt_ack_OR : NODE; -- Local Target Acknowledge Output Register
-- lt_ack_R : DFFE; -- Local Target Acknowledge Signal
-- lt_ack_R_r1 : DFFE; -- Local Target Acknowledge Register 1 Signal
-- lt_ack_R_r2 : DFFE; -- Local Target Acknowledge Register 2 Signal
-- lt_ack_R_r3 : DFFE; -- Local Target Acknowledge Register 2 Signal
-- lt_ack_R : NODE; -- Local Target Acknowledge Signal
-- lt_ack_OR : NODE; -- Local Target Acknowledge Output Register
-- lt_low_ack_R : DFFE; -- Local Target Low Acknowledge Signal
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