📄 pcic_t.tdf
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-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write State Machine is now changed to the new specification. It
-- suports:
-- 32 bit burst through lm_req32
-- 32 bit single cycle
-- 32 bit io cycle
-- 64 bit burst
-- 64 bit single cycle <-- Only if the bus contains exclusively 64 bit
-- devices
--
-- ***************** Version 26 *****************
-- User: Nprasad Date: 11/25/98 Time: 4:56p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added some comments.
--
-- ***************** Version 25 *****************
-- User: Otan Date: 11/25/98 Time: 1:33p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write Simulations Work.
--
-- ***************** Version 23 *****************
-- User: Otan Date: 11/23/98 Time: 7:04p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write debugging 64-64 and 32-64.
--
-- ***************** Version 22 *****************
-- User: Otan Date: 11/23/98 Time: 3:51p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Read Simulations successful. Added 64-bit -> 64-bit and 32-bit
-- -> 64-bit transactions.
--
-- ***************** Version 21 *****************
-- User: Nprasad Date: 11/23/98 Time: 11:32a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixed 32-->64 State Machine in Target.
--
-- ***************** Version 20 *****************
-- User: Otan Date: 11/23/98 Time: 10:19a
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 19 *****************
-- User: Otan Date: 11/20/98 Time: 7:21p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 64-bit Target Read Debugging
--
-- ***************** Version 18 *****************
-- User: Otan Date: 11/20/98 Time: 4:20p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 64-bit Target Write and Memory Read works with simulation, local and
-- PCI wait states.
-- Added l_ldata_ackn and l_hdata_ackn to distinguish low and high dwords
-- for 32-bit PCI.
--
-- ***************** Version 17 *****************
-- User: Otan Date: 11/19/98 Time: 1:55p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 32-bit finished, except for data timeout.
--
-- ***************** Version 16 *****************
-- User: Otan Date: 11/18/98 Time: 7:51p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read/Write works for single and burst cycles for PCI and local
-- wait states.
--
-- ***************** Version 15 *****************
-- User: Otan Date: 11/17/98 Time: 10:27p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read simulating successfully, except for lm_ackn
--
-- ***************** Version 14 *****************
-- User: Nprasad Date: 11/17/98 Time: 8:34p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added 64 bit place holders for all of the files. Completed par gen and
-- parity check for 64 bit.
--
-- ***************** Version 13 *****************
-- User: Nprasad Date: 11/16/98 Time: 10:05p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed Master Datapath to the top level. Added the extra signals
-- needed.
--
-- ***************** Version 12 *****************
-- User: Otan Date: 11/16/98 Time: 2:54p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 11 *****************
-- User: Otan Date: 11/16/98 Time: 2:44p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Read Hold Registers Implemented.
-- Changed the ad_ce_nc=trg_ador_ena.
-- Target Read/Write single and burst cycle simulations with local and PCI
-- wait states successful.
--
-- ***************** Version 10 *****************
-- User: Otan Date: 11/15/98 Time: 10:36p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 9 *****************
-- User: Otan Date: 11/14/98 Time: 7:13p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Working on Master Read
--
-- ***************** Version 8 *****************
-- User: Otan Date: 11/14/98 Time: 1:07p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added low_data_out_hr[31..0] for the Hold Register Output Data.
-- Added low_data_out_hr_R[31..0] for the Hold Register (DFFE).
-- Added hr_dat_sel to select the Hold Register Output Data.
-- Target Read Successfully Simulated with Local and PCI wait states.
--
-- ***************** Version 6 *****************
-- User: Nprasad Date: 11/12/98 Time: 11:49p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed the output data path to the top level. Change the CE for the
-- input Ad registers so that data and command are till the next cycle.
-- Changed the Target local read state machine and the rest of the signals
-- to adjust for the change in the datapath. First draft for target local
-- read. Minor tweaks elsewhere.
--
-- ***************** Version 5 *****************
-- User: Otan Date: 11/12/98 Time: 6:20p
-- Updated in $/MegaCore/HandOff/45/source/src
-- target write simulated successfully
--
-- ***************** Version 4 *****************
-- User: Nprasad Date: 11/11/98 Time: 10:28p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target local write data path complete. Target local write state machine
-- complete. Signals were modified to fucntion as specified. First draft.
--
-- ***************** Version 3 *****************
-- User: Nprasad Date: 11/11/98 Time: 7:11p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Address path has changed. Data path is through a partial change.
-- New signal names added. Other superficial changes.
--
-- ***************** Version 2 *****************
-- User: Nprasad Date: 10/26/98 Time: 11:28a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Removed PCI_B Optimization
--
-- ***************** Version 1 *****************
-- User: Ziada Date: 10/22/98 Time: 4:34p
-- Created in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 70 *****************
-- User: Otan Date: 10/21/98 Time: 9:29a
-- Updated in $/MegaCore/HandOff/40/source/src
-- Added lt_abortn to TS_LRD_WAIT for devseln and stopn. Added lt_abortn
-- to LR_PXFR and LR_PXFR1 for trdyn.
--
-- Function prototype for pcic_c: pci_b configuration Module
FUNCTION pcic_c (clk, rstn, cben_ir[3..0], ad_ir[31..0], adr_phase, cfg_dat_vld, serr_det,
adr_dec_ena, tabrt_set, tabrt_rcvd_set, mabrt_set, bar_hit_rst, perr_det_set,
perr_rep_set, lcfg_adr[7..0], lcfg_ben[3..0], lcfg_dat_in[31..0], lcfg_adr_vld,
lcfg_dat_vld, dac_cfg, ad_ir_addr[31..0], cben_ir_addr[3..0])
WITH (LOCAL_CONFIG_ENA, HOST_BRIDGE_ENA, VENDOR_ID, DEVICE_ID, REVISION_ID, CLASS_CODE,
SUBSYSTEM_ID, SUBSYSTEM_VENDOR_ID, MIN_GRANT, MAX_LATENCY, BAR0, BAR1,
BAR2, BAR3, BAR4, BAR5, NUMBER_OF_BARS)
RETURNS (mem_bar_hit, io_bar_hit, cfg_dat_out[31..0], io_ena, mem_ena, mstr_ena, mwi_ena,
perr_ena, serr_ena, perr_rep, tabrt_sig, tabrt_rcvd, mabrt_rcvd, serr_sig,
perr_det, lat_dat[7..0], cache_dat[7..0], base_hit[5..0], lcfg_dat_out[31..0], dac_out);--, cap_ptr_dat[7..0]);
-- Function prototype for pcic_sr: pci_b set/reset flip flop with set dominant
FUNCTION pcic_sr (s, r, clk, clrn, prn)
RETURNS (q);
% JOT
FUNCTION pcic_m (clk, rstn, gnt, low_ad_ir[31..0], high_ad_ir[31..0], frame, irdy, trdy, devsel, stop, perr, mstr_ena, lat_dat[7..0],
lm_req32, lm_last, lm_rdyn, low_lm_dati[31..0], lm_adri[31..0], low_lm_beni[3..0], ack64, high_lm_dati[31..0],
high_lm_beni[3..0], lm_cmd[3..0])
WITH (OPTIMIZE_MSTR)
RETURNS (low_data_out[31..0], high_data_out[31..0], ad_oe, ad_sel, ad_ir_ce_D, cbe_ce, low_cbe_out[3..0], high_cbe_out[3..0], cbe_oe,
frame_out, frame_oe, irdy_out, irdy_oe, req_out, perr_vld, perr_oe, par_oe, perr_rep_set, targ_abrt_set, mstr_abrt_set,
lm_ackn, trdyrn, low_lm_dato[31..0], lm_tsr[8..0], mstr_actv, hr_dat_sel, dati_HR_ena, ADOR_ena, hr_cbe_sel, cbe_HR_ena,
req64_out, req64_oe, high_lm_dato[31..0], hr_adr_sel);
%
FUNCTION pcic_m (clk, rstn, gnt, frame, irdy, trdy, devsel, stop, perr, mstr_ena, lat_dat[7..0],
lm_req64, lm_req32, lm_last, lm_rdyn, low_lm_dati[31..0], lm_adri[31..0], low_lm_beni[3..0], ack64, high_lm_dati[31..0],
high_lm_beni[3..0], lm_cmd[3..0]%64bit_PCI%)
WITH (OPTIMIZE_MSTR)
RETURNS (low_data_out[31..0], high_data_out[31..0], ad_oe, ad_sel, ad_ir_ce_D, cbe_ce, low_cbe_out[3..0], high_cbe_out[3..0], cbe_oe,
frame_out, frame_oe, irdy_out, irdy_oe, req_out, perr_vld, perr_oe, par_oe, perr_rep_set, targ_abrt_set, mstr_abrt_set,
lm_adr_ackn, lm_ackn, %trdyrn,% lm_tsr[9..0], mstr_actv, hr_dat_sel, dati_HR_ena, ADOR_ena, hr_cbe_sel, cbe_HR_ena,
req64_out, req64_oe, hr_adr_sel, lm_ldata_ackn, lm_hdata_ackn, lm_dxfrn, ADOR_HI_DENA, HI_LOW_SEL, 64_trans_out, ad_ir_ce_a, cben_ir_ce_a,
cben_ir_ce_d, dac_decode_out);
INCLUDE "maxplus2.inc";
PARAMETERS
(
CAP_LIST_ENA = "NO",
HOST_BRIDGE_ENA = "NO",
DATA_TIMEOUT = 16, -- Timeout length
OPTIMIZE_TARG = "YES"
);
CONSTANT DATA_TIMEOUT_WIDTH = CEIL(LOG2(DATA_TIMEOUT-1));
subdesign 'pcic_t'
(
-- PCI Signal Inputs
clk : INPUT; -- PCI Clock
rstn : INPUT; -- PCI Reset
ad_ir_address[31..0] : INPUT; -- AD Input Registers Address
ad_ir_data[31..0] : INPUT;
cben_ir_data[3..0] : INPUT;
cben_IR_address[3..0] : INPUT; -- Command/Byte Enable Input Registers
frame : INPUT; -- Active High FRAMEn Input
irdy : INPUT; -- Active High IRDYn Input
idsel : INPUT; -- IDSEL Input Register
req64 : INPUT; -- Request 64 bit transactions
-- Local Side Inputs
low_lt_dati[31..0] : INPUT; -- Local Target Data Input
high_lt_dati[31..0] : INPUT; -- Local Target Data Input
lt_rdyn : INPUT; -- Local Target Ready Input
lt_discn : INPUT; -- Local Target Disconnect Input
lt_abortn : INPUT; -- Local Target Abort Input
-- 64bit_PCI : INPUT; -- Indicates a pure 64 bit system
perr_rep_set : INPUT; -- Data Parity Error Signaled
perr_det_set : INPUT; -- Parity Error Detected
serr_sig_set : INPUT; -- System Parity Error Signaled
mstr_actv : INPUT; -- Master is Active. Has PCI Bus.
mstr_dac_decode : INPUT;
mstr_abrt_set : INPUT; -- Master Abort Set
targ_abrt_set : INPUT; -- Target Abort Set
lm_ackn : INPUT;
-- cap_ptr_dat[7..0] : INPUT;
serr_vld : OUTPUT; -- SERR valid
perr_vld : OUTPUT; -- Parity Error was detected
perr_oe : OUTPUT; -- PERR Output Enable
par_oe : OUTPUT; -- PAR Output Enable
-- Local Side Outputs
lt_dxfrn : OUTPUT; -- Target data transfer is occurring
lt_tsr[11..0] : OUTPUT; -- Target Transaction Status Registers
-- 5..0: Target Base Address Register accessed
-- 6: Target indicates an Expansion ROM hit
-- 7: Target transaction is 64 bit
-- 8: Target is accessed from PCI bus
-- 9: Burst
-- 10: I/O Cycle
lt_adr[63..0] : OUTPUT; -- Local Target Address
lt_cmd[3..0] : OUTPUT; -- Local Target Command
low_lt_ben[3..0] : OUTPUT; -- Local Target Byte Enables
high_lt_ben[3..0] : OUTPUT; -- Local Target Byte Enables
lt_framen : OUTPUT; -- Local Target Frame
lt_ackn : OUTPUT; -- Local target Acknowledge
lt_ldata_ackn : OUTPUT; -- Local low output data acknowledge
lt_hdata_ackn : OUTPUT; -- Local high output data acknowledge
irdyrn : OUTPUT; -- This is a registered version of PCI irdyn signal
-- AD Bus Controls
low_data_out[31..0] : OUTPUT; -- Local Side Low Output Data to AD Output Register
high_data_out[31..0]: OUTPUT; -- Local Side High Output Data to AD Output Register
cfg_dat_out[31..0] : OUTPUT; -- Configuration data Output to AD Output Register
cfg_cyc_out : OUTPUT; -- Configuratiob Cycle Indicator
hr_dat_sel : OUTPUT; -- Holding Register Select Signal
hi_low_sel : OUTPUT; -- Select the high data or the low data
dati_HR_ena : OUTPUT; -- Holding Register Enable Signal
ad_oe : OUTPUT; -- Target AD OE Output
ad_sel : OUTPUT; -- Target AD Output Mux Select
ad_IR_ce_A : OUTPUT; -- AD Input Register Clock Enable Address
ad_IR_ce_D : OUTPUT; -- AD Input Register Clock Enable Data
cben_IR_ce_A : OUTPUT; -- CBEn Input Register Clock Enable Address
cben_IR_ce_D : OUTPUT; -- CBEn Input Register Clock Enable Data
-- Target Control Signal Outputs
targ_oeR : OUTPUT; -- Output Enable Signal for Target Controls
trdy_out : OUTPUT; -- PCI Target Ready Output
devsel_out : OUTPUT; -- PCI Device Select Output
stop_out : OUTPUT; -- PCI Stop Output
ack64_out : OUTPUT; -- PCI Ack64 Output
-- Local Command Register Outputs
io_ena : OUTPUT; -- I/O Space Enable
mem_ena : OUTPUT; -- Memory Space Enable
mstr_ena : OUTPUT; -- Bus Master Enable
mwi_ena : OUTPUT; -- Memory Write and Invalidate Enable
perr_ena : OUTPUT; -- Pariy Error Response Enable
serr_ena : OUTPUT; -- SERR Enable
-- Local Status Register Outputs
cfg_perr_rep : OUTPUT; -- Data Parity Error Signaled
cfg_tabrt_sig : OUTPUT; -- Signaled Target Abort
cfg_tabrt_rcvd : OUTPUT; -- Recieved Target Abort
cfg_mabrt_rcvd : OUTPUT; -- Recieved Master Abort
cfg_serr_sig : OUTPUT; -- Signaled SERR
cfg_perr_det : OUTPUT; -- Detected Parity Error
-- Other Local Configuration Register Outputs
lat_dat[7..0] : OUTPUT; -- Latency Timer Register Data
cache_dat[7..0] : OUTPUT; -- Cache Line Register Data
base_hit[5..0] : OUTPUT; -- Base Address Register Comparison Outputs
-- Local Side Configuration Space Support
lcfg_adr[7..0] : INPUT = GND; -- Local Configuration Address
lcfg_ben[3..0] : INPUT = GND; -- Local Configuration Byte enables
lcfg_dat_in[31..0] : INPUT = GND; -- Local Configuration Data Input Bus
lcfg_adr_vld : INPUT = GND; -- Local Configuration Address Valid
lcfg_dat_vld : INPUT = GND; -- Local Configuration data Valid
lcfg_wr_rdn : INPUT = GND; -- Local Configuration Write/Readn 1= write, 0 = read
lcfg_dat_out[31..0] : OUTPUT; -- Local Configuration Data Output
-- For CE on top level
ADOR_ena : output; -- AD output register enable
ador_hi_dena : output; -- AD high output register disable
lt_sel_w : output; -- Local Target Write Indicator
64_trans_out : output;
adr_phase_out : OUTPUT;
dac_sr_out : OUTPUT;
-- lt_lackn : OUTPUT;
-- lt_hackn : OUTPUT;
)
VARIABLE
-- Target Control Signal Outputs
-- par_oeR : DFFE; -- Output Enable Signal for par
targ_oeR_reg : DFFE; -- Output Enable Signal for Target Controls
-- targ_oeR_reg_lc[5..1] : LCELL;
targ_oeR_reg_lc[4..1] : LCELL;
trdy_OR : node; -- PCI Target Ready Output
trdy_R : NODE; -- PCI Target Ready Output
trdy_R_not : DFFE;
trdy_R_not_lc : NODE;
-- devsel_OR : DFFE; -- PCI Device Select Output
devsel_OR : DFFE; -- PCI Device Select Output
devsel_OR_lc1 : NODE;
devsel_OR_lc2 : NODE;
devsel_OR_lc3 : NODE;
devsel_OR_lc4 : NODE;
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