📄 pcic_m.tdf
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ELSIF (trdy and direct_xfr and last_xfr) THEN
mw_sm = MW_LAST;
MW_LAST_d = VCC;
ELSE
mw_sm = MW_WAIT;
MW_WAIT_d = VCC;
END IF;
-- Master Write Last XFR. Final Data Phase. Only AD_OR Has VLD Data
-- frame is deasserted, irdy is asserted, lm_ackn is deasserted
WHEN MW_LAST => IF (trdy) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN -- Master Abort
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF(not trdy and stop) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSE
mw_sm = MW_LAST;
MW_LAST_d = VCC;
END IF;
-- Master Write Hold. Wait for devsel. Only AD_OR Has VLD Data
-- frame is asserted, irdy is deasserted, lm_ackn is deasserted
WHEN MW_HOLD => IF (stop) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devselR and ack64R) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSIF (devselR and not ack64R) THEN
mw_sm = MW_DXFR_32;
MW_DXFR_32_d= VCC;
ELSE
mw_sm = MW_HOLD;
MW_HOLD_d = VCC;
END IF;
-- Master Write 32 bit Data Transfer. Transfer lower bits. AD_OR High and Low Has VLD Data
-- frame is asserted, irdy is asserted, lm_ackn is asserted
WHEN MW_DXFR_32 => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (!trdy and !lm_rdynR) THEN -- PCI wait, Local ready
mw_sm = MW_WAIT;
MW_WAIT_d = VCC;
ELSIF (!trdy and lm_rdynR) THEN -- PCI wait, Local wait
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
-- This transition has a problem. It requires lm_last to be valid only for one clock
-- This transition needs to be taken on the 2nd xfr after lm_last is asserted.
-- ELSIF (trdy and lm_rdynR and (last_xfr and not lm_last)) THEN -- pci ready, local wait, last xfr
-- mw_sm = MW_LAST;
-- MW_LAST_d = VCC;
ELSIF (trdy and (last_xfr and not lm_last)) THEN -- pci ready, local wait, last xfr
mw_sm = MW_LAST; -- mmbw64_pwpd_1a.scf
MW_LAST_d = VCC;
ELSIF (trdy and !lm_rdynR) THEN -- PCI ready, local ready
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
ELSE --trdy and lm_rdynR and (!last_xfr or lm_last)
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
END IF;
-- Master Write Wait 32 bit Data Transfer. Transfer high bits from previous word.
-- AD_OR High and Low Has VLD Data and AD_HR Low has Data
-- frame is asserted, irdy is asserted, lm_ackn is deasserted
WHEN MW_WAIT_32 => IF (stop) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (trdy and not latcntr_toR) THEN
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
ELSIF (trdy and latcntr_toR) THEN
mw_sm = MW_LAST;
MW_LAST_d = VCC;
ELSE
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
END IF;
-- Master Write End. All data has been transferred
WHEN MW_END => mw_sm = MW_IDLE;
MW_IDLE_d = VCC;
END CASE;
ELSE GENERATE
CASE mw_sm IS
-- Master Write Idle
WHEN MW_IDLE => IF (MS_ENA and (low_lm_beni[0] and not dac_decode_d) )THEN -- ZA changed the transition because cmmand is only available in MS_ENA not before
--IF (MS_ADR_d and write) THEN
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
ELSIF (MS_ENA and (high_lm_beni[0] and dac_decode_d )) THEN
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
ELSE
mw_sm = MW_IDLE;
MW_IDLE_d = VCC;
END IF;
--
-- Master Write Local XFR. Pipe is Empty
-- Waiting for the first word to be recieved from the local side
-- frame is asserted, irdy is deasserted, lm_ack is asserted.
--
WHEN MW_LXFR => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN -- Master Abort
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (!lm_rdynR and !direct_xfr and devselR) THEN -- Local side is ready, data is transferred
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
ELSIF (!lm_rdynR and !direct_xfr and not devselR) THEN
mw_sm = MW_HOLD;
MW_HOLD_d = VCC;
ELSIF (!lm_rdynR and direct_xfr and !last_xfr) THEN -- It is a direct transfer adn it is not the last transfer
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSIF (!lm_rdynR and direct_xfr and last_xfr) THEN -- It is a direct transfer and it is a last transfer
mw_sm = MW_LAST;
MW_LAST_d = VCC;
ELSE -- Local Side needs to transfer the data
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
END IF;
-- Master Write Data Xfr. ( Only AD_OR Has valid Data)
-- frame is asserted, irdy is asserted, lm_ackn is asserted
WHEN MW_DXFR => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN -- Master Abort
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (lm_rdynR and trdy) THEN
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
ELSIF (lm_rdynR and not trdy and not last_xfr) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSIF (!direct_xfr and trdy) THEN
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
ELSIF (!direct_xfr and not trdy) THEN
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
ELSIF (!last_xfr and trdy) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
-- ELSIF (!last_xfr and not trdy) THEN
-- mw_sm = MW_WAIT;
-- MW_WAIT_d = VCC;
ELSIF (not trdy) THEN
mw_sm = MW_WAIT;
MW_WAIT_d = VCC;
ELSIF (last_xfr and trdy) THEN
mw_sm = MW_LAST;
MW_LAST_d = VCC;
ELSE
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
END IF;
-- Master Write Wait. PCI Asserted wait Both AD_OR and AD_HR have vld Data
-- frame is asserted, irdy is asserted, lm_ackn is deasserted
WHEN MW_WAIT => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (trdy and !direct_xfr) THEN
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
ELSIF (trdy and direct_xfr and !last_xfr) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSIF (trdy and direct_xfr and last_xfr) THEN
mw_sm = MW_LAST;
MW_LAST_d = VCC;
ELSE
mw_sm = MW_WAIT;
MW_WAIT_d = VCC;
END IF;
-- Master Write Last XFR. Final Data Phase. Only AD_OR Has VLD Data
-- frame is deasserted, irdy is asserted, lm_ackn is deasserted
WHEN MW_LAST => IF (trdy) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN -- Master Abort
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF(not trdy and stop) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSE
mw_sm = MW_LAST;
MW_LAST_d = VCC;
END IF;
-- Master Write Hold. Wait for devsel. Only AD_OR Has VLD Data
-- frame is asserted, irdy is deasserted, lm_ackn is deasserted
WHEN MW_HOLD => IF (stop) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devselR and ack64R) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSIF (devselR and not ack64R) THEN
mw_sm = MW_DXFR_32;
MW_DXFR_32_d= VCC;
ELSE
mw_sm = MW_HOLD;
MW_HOLD_d = VCC;
END IF;
-- Master Write 32 bit Data Transfer. Transfer lower bits. AD_OR High and Low Has VLD Data
-- frame is asserted, irdy is asserted, lm_ackn is asserted
WHEN MW_DXFR_32 => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (!trdy and !lm_rdynR) THEN -- PCI wait, Local ready
mw_sm = MW_WAIT;
MW_WAIT_d = VCC;
ELSIF (!trdy and lm_rdynR) THEN -- PCI wait, Local wait
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
-- This transition has a problem. It requires lm_last to be valid only for one clock
-- This transition needs to be taken on the 2nd xfr after lm_last is asserted.
-- ELSIF (trdy and lm_rdynR and (last_xfr and not lm_last)) THEN -- pci ready, local wait, last xfr
-- mw_sm = MW_LAST;
-- MW_LAST_d = VCC;
ELSIF (trdy and (last_xfr and not lm_last)) THEN -- pci ready, local wait, last xfr
mw_sm = MW_LAST; -- mmbw64_pwpd_1a.scf
MW_LAST_d = VCC;
ELSIF (trdy and !lm_rdynR) THEN -- PCI ready, local ready
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
ELSE --trdy and lm_rdynR and (!last_xfr or lm_last)
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
END IF;
-- Master Write Wait 32 bit Data Transfer. Transfer high bits from previous word.
-- AD_OR High and Low Has VLD Data and AD_HR Low has Data
-- frame is asserted, irdy is asserted, lm_ackn is deasserted
WHEN MW_WAIT_32 => IF (stop) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (trdy and not latcntr_toR) THEN
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
ELSIF (trdy and latcntr_toR) THEN
mw_sm = MW_LAST;
MW_LAST_d = VCC;
ELSE
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
END IF;
-- Master Write End. All data has been transferred
WHEN MW_END => mw_sm = MW_IDLE;
MW_IDLE_d = VCC;
END CASE;
END GENERATE;
%
MW_IDLE_d = (MW_IDLE and not ((MS_ENA and lm_cmd[0])))
OR (MW_END);
MW_LXFR_d = (MW_IDLE and (MS_ENA and lm_cmd[0]))
OR (MW_LXFR and (not (stop) or not (devsel_toR)) and not (!lm_rdynR and !direct_xfr and devselR) and not (!lm_rdynR and !direct_xfr and not devselR)
and not (!lm_rdynR and direct_xfr and !last_xfr) and not (!lm_rdynR and direct_xfr and last_xfr))
OR (MW_DXFR and (not (stop) or not (devsel_toR)) and (lm_rdynR and trdy));
MW_DXFR_d = (MW_LXFR and (not (stop) or not (devsel_toR)) and not (!lm_rdynR and !direct_xfr and devselR) and not (!lm_rdynR and !direct_xfr and not devselR)
and (!lm_rdynR and direct_xfr and !last_xfr))
OR (MW_DXFR and (not (stop) or not (devsel_toR)) and not (lm_rdynR and trdy) and not (lm_rdynR and not trdy) and not (!direct_xfr and trdy)
and not (!direct_xfr and not trdy) and not (!last_xfr and trdy) and not (!last_xfr and not trdy) and not (last_xfr and trdy))
OR (MW_WAIT and not (stop) and not (trdy and !direct_xfr) and (trdy and direct_xfr and !last_xfr))
OR (MW_HOLD and (not (stop) or not (devsel_toR)) and (devselR and ack64R))
OR (MW_DXFR_32 and not (stop) and not (!trdy and !lm_rdynR) and not (!trdy and lm_rdynR) and not (trdy and lm_rdynR and (last_xfr and not lm_last))
and not (trdy and !lm_rdynR));
MW_WAIT_d = (MW_DXFR and (not (stop) or not (devsel_toR)) and not (lm_rdynR and trdy) and not (lm_rdynR and not trdy) and not (!direct_xfr and trdy)
and not (!direct_xfr and not trdy) and not (!last_xfr and trdy) and (!last_xfr and not trdy))
OR (MW_WAIT and not (stop) and not (trdy and !direct_xfr) and not (trdy and direct_xfr and !last_xfr) and not (trdy and direct_xfr and last_xfr))
OR (MW_DXFR_32 and not (stop) and (!trdy and !lm_rdynR));
MW_LAST_d = (MW_LXFR and (not (stop) or not (devsel_toR)) and not (!lm_rdynR and !direct_xfr and devselR) and not (!lm_rdynR and !direct_xfr and not devselR)
and not (!lm_rdynR and direct_xfr and !last_xfr) and (!lm_rdynR and direct_xfr and last_xfr))
OR (MW_DXFR and (not (stop) or not (devsel_toR)) and not (lm_rdynR and trdy) and not (lm_rdynR and not trdy) and not (!direct_xfr and trdy)
and not (!direct_xfr and not trdy) and not (!last_xfr and trdy) and not (!last_xfr and not trdy) and (last_xfr and trdy))
OR (MW_WAIT and not (stop) and not (trdy and !direct_xfr) and not (trdy and direct_xfr and !last_xfr) and (trdy and direct_xfr and last_xfr))
OR (MW_LAST and (not (trdy) or not (devsel_toR) or not (not trdy and stop)))
OR (MW_DXFR_32 and not (stop) and not (!trdy and !lm_rdynR) and not (!trdy and lm_rdynR) and (trdy and lm_rdynR and (last_xfr and not lm_last)));
MW_HOLD_d = (MW_LXFR and (not (stop) or (devsel_toR)) and not (!lm_rdynR and !direct_xfr and devselR) and (!lm_rdynR and !direct_xfr and not devselR))
OR (MW_HOLD and (not (stop) or not (devsel_toR)) and not (devselR and ack64R) and not (devselR and not ack64R));
MW_DXFR_32_d = (MW_LXFR and (not (stop) or not (devsel_toR)) and (!lm_rdynR and !direct_xfr and devselR))
OR (MW_DXFR and (not (stop) or not (devsel_toR)) and not (lm_rdynR and trdy) and not (lm_rdynR and not trdy) and (!direct_xfr and trdy))
OR (MW_HOLD and (not (stop) or not (devsel_toR)) and not (devselR and ack64R) and (devselR and not ack64R))
OR (MW_DXFR_32 and not (stop) and not (!trdy and !lm_rdynR) and (!trdy and lm_rdynR))
OR (MW_WAIT_32 and not (stop) and trdy);
MW_WAIT_32_d = (MW_DXFR and (not (stop) or not (devsel_toR)) and not (lm_rdynR and trdy) and not (lm_rdynR and not trdy) and not (!direct_xfr and trdy) and (!direct_xfr and not trdy))
OR (MW_WAIT and not (stop) and (trdy and !direct_xfr))
OR (MW_DXFR_32 and not (stop) and not (!trdy and !lm_rdynR) and not (!trdy and lm_rdynR) and not (trdy and lm_rdynR and (last_xfr and not lm_last)) and (trdy and !lm_rdynR))
OR (MW_WAIT_32 and not (stop) and not (trdy));
MW_END_d = (MW_LXFR and ((stop) or (devsel_toR)))
OR (MW_DXFR and ((stop) or (devsel_toR)))
OR (MW_WAIT and (stop))
OR (MW_LAST and ((trdy) or (devsel_toR) or (not trdy and stop)))
OR (MW_HOLD and ((stop) or (devsel_toR)))
OR (MW_DXFR_32 and (stop))
OR (MW_WAIT_32 and (stop)) ;
%
-- Master Read state machine
mr_sm.clk = clk;
mr_sm.reset = not rstn;
case mr_sm IS
WHEN MR_IDLE => IF (MS_ADR and NOT write and not last_xfr and not dac_decode) THEN
mr_sm = MR_PXFR;
MR_PXFR_d = VCC;
ELSIF (MS_ADR and not write and last_xfr and not dac_decode) THEN
mr_sm = MR_LPXFR;
MR_LPXFR_d = VCC;
ELSIF (MS_ADR2 and NOT write and not last_xfr and dac_decode%dac_decodeR_R_q%) THEN
mr_sm = MR_PXFR;
MR_PXFR_d = VCC;
ELSIF (MS_ADR2 and not write and last_xfr and dac_decode%dac_decodeR_R_q%) THEN
mr_sm = MR_LPXFR;
MR_LPXFR_d = VCC;
ELSE
mr_sm = MR_IDLE;
MR_IDLE_d = VCC;
END IF;
--MR_IDLE and (MS_ADR2 and NOT write and not last_xfr and dac_decode)
-- and (not MS_ADR or write or last_xfr or dac_decode)
-- and (not MS_ADR or write or not last_xfr or dac_decode)
-- Wait to recieve First PCI WORD
-- irdy is asserted, Frame is asserted, and lm_ack is deasserted
WHEN MR_PXFR => IF (devsel_toR) THEN
mr_sm = MR_END; -- End State Machine
MR_END_d = ⌨️ 快捷键说明
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