📄 pcic_m.tdf
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ELSE
mstr_sm = MS_IDLE;
MS_IDLE_d = VCC;
END IF;
-- Master Request. Master Asserting reqn PCI Output
WHEN MS_REQ => IF (park) THEN
mstr_sm = MS_ENA;
MS_ENA_d = VCC;
ELSE
mstr_sm = MS_REQ;
MS_REQ_d = VCC;
END IF;
-- Master Enable. All Output enables for PCI signals are Turned ON
WHEN MS_ENA => IF (gnt) THEN
mstr_sm = MS_ADR;
MS_ADR_d = VCC;
ELSE
mstr_sm = MS_REQ;
MS_REQ_d = VCC;
END IF;
-- Master Address. Address Phase
WHEN MS_ADR => IF (not dac_decode) THEN
mstr_sm = MS_DXFR;
MS_DXFR_d = VCC;
ELSE
mstr_sm = MS_ADR2;
MS_ADR2_d = VCC;
END IF;
-- Master Address. Dual Address Cycle for 64-bit Addressing
WHEN MS_ADR2 => mstr_sm = MS_DXFR;
MS_DXFR_d = VCC;
-- Master Park. Arbitor Requested Parking of Bus, All Output Enables
-- Are turned on and All control Signals are De-Asserted.
WHEN MS_PARK => IF (gnt and (lm_req64 # lm_req32) and lm_ackn) THEN
mstr_sm = MS_ENA; -- I used MS_ENA because the AD_ce would use this
MS_ENA_d = VCC; -- transition.
ELSIF (not gnt and (lm_req64 # lm_req32) and lm_ackn) THEN
mstr_sm = MS_REQ;
MS_REQ_d = VCC;
ELSIF (not gnt) THEN
mstr_sm = MS_IDLE;
MS_IDLE_d = VCC;
ELSE
mstr_sm = MS_PARK;
MS_PARK_d = VCC;
END IF;
-- Maste Data Transfer. Read/Write State Machine is Active.
WHEN MS_DXFR => IF (mstr_done) THEN
mstr_sm = MS_TAR;
MS_TAR_d = VCC;
ELSE
mstr_sm = MS_DXFR;
MS_DXFR_d = VCC;
END IF;
-- Master Turn Around State. Deassert All PCI Signals
WHEN MS_TAR => mstr_sm = MS_IDLE;
MS_IDLE_d = VCC;
%
MS_IDLE_d = (MS_IDLE and not ((mstr_ena and (lm_req64 # lm_req32))) and not (park))
OR (MS_PARK and not ((gnt and (lm_req64 # lm_req32)) and not (not gnt and (lm_req64 # lm_req32)) and (not gnt))
OR (MS_TURN_AR);
MS_REQ_d = (MS_IDLE and (mstr_ena and (lm_req64 # lm_req32)))
OR (MS_REQ and not (park))
OR (MS_ENA and not (gnt))
OR (MS_PARK and not ((gnt and (lm_req64 # lm_req32)) and (not gnt and (lm_req64 # lm_req32)));
MS_ENA_d = (MS_REQ and park)
OR (MS_PARK and (gnt and (lm_req64 # lm_req32)));
MS_ADR_d = (MS_ENA and (gnt));
MS_PARK_d = (MS_IDLE and not ((mstr_ena and (lm_req64 # lm_req32))) and (park))
OR (MS_PARK and not ((gnt and (lm_req64 # lm_req32))) and not ((not gnt and (lm_req64 # lm_req32))) and not ((not gnt));
MS_DXFR_d = (MS_ADR)
OR (MS_DXFR and not (mstr_done));
MS_TAR_d = (MS_DXFR and mstr_done);
%
END CASE;
-- Master Write State Machine
mw_sm.clk = clk;
mw_sm.reset = not rstn;
%CASE mw_sm IS
-- Master Write Idle
WHEN MW_IDLE => IF (MS_ENA and lm_cmd[0]) THEN -- ZA changed the transition because cmmand is only available in MS_ENA not before
--IF (MS_ADR_d and write) THEN
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
ELSE
mw_sm = MW_IDLE;
MW_IDLE_d = VCC;
END IF;
--
-- Master Write Local XFR. Pipe is Empty
-- Waiting for the first word to be recieved from the local side
-- frame is asserted, irdy is deasserted, lm_ack is asserted.
--
WHEN MW_LXFR => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN -- Master Abort
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (!lm_rdynR) THEN -- Local side is ready, data is transferred
IF (!direct_xfr) THEN -- Need muxing because ack64 is not asserted
IF (devselR) THEN -- Devsel is asserted
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
ELSE -- Waiting for Devsel
mw_sm = MW_HOLD;
MW_HOLD_d = VCC;
END IF;
ELSIF (!last_xfr) THEN -- It is a direct transfer adn it is not the last transfer
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSE -- It is a direct transfer and it is a last transfer
mw_sm = MW_LAST;
MW_LAST_d = VCC;
END IF;
ELSE -- Local Side needs to transfer the data
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
END IF;
-- Master Write Data Xfr. ( Only AD_OR Has valid Data)
-- frame is asserted, irdy is asserted, lm_ackn is asserted
WHEN MW_DXFR => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN -- Master Abort
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (lm_rdynR) THEN
IF (trdy) THEN
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
ELSE
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
END IF;
ELSIF (!direct_xfr) THEN
IF (trdy) THEN
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
ELSE
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
END IF;
ELSIF (!last_xfr) THEN
IF (trdy) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSE
mw_sm = MW_WAIT;
MW_WAIT_d = VCC;
END IF;
ELSE
IF (trdy) THEN
mw_sm = MW_LAST;
MW_LAST_d = VCC;
ELSE
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
END IF;
END IF;
-- Master Write Wait. PCI Asserted wait Both AD_OR and AD_HR have vld Data
-- frame is asserted, irdy is asserted, lm_ackn is deasserted
WHEN MW_WAIT => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (trdy) THEN
IF (!direct_xfr) THEN
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
ELSIF (!last_xfr) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSE
mw_sm = MW_LAST;
MW_LAST_d = VCC;
END IF;
ELSE
mw_sm = MW_WAIT;
MW_WAIT_d = VCC;
END IF;
-- Master Write Last XFR. Final Data Phase. Only AD_OR Has VLD Data
-- frame is deasserted, irdy is asserted, lm_ackn is deasserted
WHEN MW_LAST => IF (trdy) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN -- Master Abort
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF(not trdy and stop) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSE
mw_sm = MW_LAST;
MW_LAST_d = VCC;
END IF;
-- Master Write Hold. Wait for devsel. Only AD_OR Has VLD Data
-- frame is asserted, irdy is deasserted, lm_ackn is deasserted
WHEN MW_HOLD => IF (stop) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devselR) THEN
IF (ack64R) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSE
mw_sm = MW_DXFR_32;
MW_DXFR_32_d= VCC;
END IF;
ELSE
mw_sm = MW_HOLD;
MW_HOLD_d = VCC;
END IF;
-- Master Write 32 bit Data Transfer. Transfer lower bits. AD_OR High and Low Has VLD Data
-- frame is asserted, irdy is asserted, lm_ackn is asserted
WHEN MW_DXFR_32 => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (!trdy and !lm_rdynR) THEN -- PCI wait, Local ready
mw_sm = MW_WAIT;
MW_WAIT_d = VCC;
ELSIF (!trdy and lm_rdynR) THEN -- PCI wait, Local wait
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
-- This transition has a problem. It requires lm_last to be valid only for one clock
-- This transition needs to be taken on the 2nd xfr after lm_last is asserted.
ELSIF (trdy and lm_rdynR and (last_xfr and not lm_last)) THEN -- pci ready, local wait, last xfr
mw_sm = MW_LAST;
MW_LAST_d = VCC;
ELSIF (trdy and !lm_rdynR) THEN -- PCI ready, local ready
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
ELSE --trdy and lm_rdynR and (!last_xfr or lm_last)
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
END IF;
-- Master Write Wait 32 bit Data Transfer. Transfer high bits from previous word.
-- AD_OR High and Low Has VLD Data and AD_HR Low has Data
-- frame is asserted, irdy is asserted, lm_ackn is deasserted
WHEN MW_WAIT_32 => IF (stop) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (trdy) THEN
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
ELSE
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
END IF;
-- Master Write End. All data has been transferred
WHEN MW_END => mw_sm = MW_IDLE;
MW_IDLE_d = VCC;
END CASE;%
IF (DUAL_ADDRESS_ENA == "NO") GENERATE
CASE mw_sm IS
-- Master Write Idle
WHEN MW_IDLE => IF (MS_ENA and (lm_cmd[0])) THEN -- ZA changed the transition because cmmand is only available in MS_ENA not before
--IF (MS_ADR_d and write) THEN
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
ELSIF (MS_ADR and (lm_cmd[0] )) THEN
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
ELSE
mw_sm = MW_IDLE;
MW_IDLE_d = VCC;
END IF;
--
-- Master Write Local XFR. Pipe is Empty
-- Waiting for the first word to be recieved from the local side
-- frame is asserted, irdy is deasserted, lm_ack is asserted.
--
WHEN MW_LXFR => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN -- Master Abort
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (!lm_rdynR and !direct_xfr and devselR) THEN -- Local side is ready, data is transferred
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
ELSIF (!lm_rdynR and !direct_xfr and not devselR) THEN
mw_sm = MW_HOLD;
MW_HOLD_d = VCC;
ELSIF (!lm_rdynR and direct_xfr and !last_xfr) THEN -- It is a direct transfer adn it is not the last transfer
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSIF (!lm_rdynR and direct_xfr and last_xfr) THEN -- It is a direct transfer and it is a last transfer
mw_sm = MW_LAST;
MW_LAST_d = VCC;
ELSE -- Local Side needs to transfer the data
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
END IF;
-- Master Write Data Xfr. ( Only AD_OR Has valid Data)
-- frame is asserted, irdy is asserted, lm_ackn is asserted
WHEN MW_DXFR => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN -- Master Abort
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (lm_rdynR and trdy) THEN
mw_sm = MW_LXFR;
MW_LXFR_d = VCC;
ELSIF (lm_rdynR and not trdy and not last_xfr) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
ELSIF (!direct_xfr and trdy) THEN
mw_sm = MW_DXFR_32;
MW_DXFR_32_d = VCC;
ELSIF (!direct_xfr and not trdy) THEN
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
ELSIF (!last_xfr and trdy) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
-- ELSIF (!last_xfr and not trdy) THEN
-- mw_sm = MW_WAIT;
-- MW_WAIT_d = VCC;
ELSIF (not trdy) THEN
mw_sm = MW_WAIT;
MW_WAIT_d = VCC;
ELSIF (last_xfr and trdy) THEN
mw_sm = MW_LAST;
MW_LAST_d = VCC;
ELSE
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
END IF;
-- Master Write Wait. PCI Asserted wait Both AD_OR and AD_HR have vld Data
-- frame is asserted, irdy is asserted, lm_ackn is deasserted
WHEN MW_WAIT => IF (stop) THEN -- Disconnect
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (devsel_toR) THEN
mw_sm = MW_END;
MW_END_d = VCC;
ELSIF (trdy and !direct_xfr) THEN
mw_sm = MW_WAIT_32;
MW_WAIT_32_d = VCC;
ELSIF (trdy and direct_xfr and !last_xfr) THEN
mw_sm = MW_DXFR;
MW_DXFR_d = VCC;
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