pcic_m.tdf

Altera AHDL语言设计的PCI总线

	MW_DXFR			: NODE;
	MW_DXFR_r1_d		: NODE;
	MW_DXFR_r2_d		: NODE;
	MW_DXFR_d			: NODE;


	
----------- Master Read State Machine -----------------------------------------


	MR_IDLE_not,
--	MR_PXFR,	
	MR_DXFR,
--	MR_LPXFR,
	MR_LWAIT,
--	MR_LLWAIT,
--	MR_LLXFR,
	MR_END			: DFFE;
								
	MR_IDLE,
	MR_IDLE_d,
--	MR_PXFR_d,	
	MR_DXFR_d,
--	MR_LPXFR_d,
	MR_LWAIT_d,
--	MR_LLWAIT_d,
--	MR_LLXFR_d,
	MR_END_d			: NODE;
	
		
	MR_PXFR_r1		: DFFE;
	MR_PXFR_r2		: DFFE;
	MR_PXFR			: NODE;
	MR_PXFR_r1_d		: NODE;
	MR_PXFR_r2_d		: NODE;
	MR_PXFR_d			: NODE;

	MR_LPXFR_r1		: DFFE;
	MR_LPXFR_r2		: DFFE;
	MR_LPXFR_r3		: DFFE;
	MR_LPXFR			: NODE;
	MR_LPXFR_r1_d		: NODE;
	MR_LPXFR_r2_d		: NODE;
	MR_LPXFR_r3_d		: NODE;
	MR_LPXFR_d		: NODE;

	MR_LLWAIT_r1		: DFFE;
	MR_LLWAIT_r2		: DFFE;
	MR_LLWAIT			: NODE;
	MR_LLWAIT_r1_d		: NODE;
	MR_LLWAIT_r2_d		: NODE;
	MR_LLWAIT_d		: NODE;
	
	MR_LLXFR_r1		: DFFE;
	MR_LLXFR_r2		: DFFE;
	MR_LLXFR			: NODE;
	MR_LLXFR_r1_d		: NODE;
	MR_LLXFR_r2_d		: NODE;
	MR_LLXFR_d		: NODE;

	
	
END GENERATE;


	

	-- Latency Timer Nodes
	latcntr : lpm_counter			-- Latency Timer Counter
		WITH (LPM_WIDTH= 8,
			LPM_DIRECTION= "DOWN");
		
	latcntr_tc			: NODE;
	latcntr_toR			: SRFF;
	
IF (DUAL_ADDRESS_ENA == "NO") GENERATE
	devsel_cntr			: lpm_counter with (LPM_WIDTH = 2, LPM_DIRECTION = "UP");
	d_gnd[1..0]			: DFFE;
ELSE GENERATE
	devsel_cntr			: lpm_counter with (LPM_WIDTH = 3, LPM_DIRECTION = "UP");
	d_gnd[2..0]			: DFFE;
END GENERATE;

	dac_decodeR			: SRFF;
--	dac_decodeR_R		: DFFE;
	dac_decode			: NODE;
	dac_decode_d		: NODE;
	dac_decode_d_lc		: NODE;
--	dac_decodeR_R_q		: NODE;

	devsel_toR			: DFFE;
	mstr_abrt			: DFFE;
	
	
	
	-- Other Master State Machine Inputs 
	park				: DFFE;		-- Indicates that PCI Bus is parked
	mstr_done 			: NODE;		-- Indicates that mstr xfr is complete
	
	
	-- Target Abort Set Register
	tabrt_set			: DFFE;
	
	-- Local Side Input Registers
    lm_rdynR			: DFFE;		-- Registered Active Low Local Ready
	lm_req64R			: SRFF;		-- Registered Active High Local request
--	lm_adr64R			: SRFF;
--jot	lm_req32R			: SRFF;		-- Registered Active High Local request



	adr_vld				: node;		-- Local Side Has the valid Address/data
		
--	write				: DFFE;		-- 1: Write Cycle, 0: Read Cycle
	write				: SRFF;		-- 1: Write Cycle, 0: Read Cycle

	io_cyc				: DFFE;		-- Command is I/O Read/Write
--	cfg_cyc				: DFFE;		-- Command is Configuration Read/Write
	cfg_cyc				: SRFF;		-- Command is Configuration Read/Write

	lm_last_R			: SRFF;		-- Last Transfer Indicator
	last_xfr			: node;		-- Last Transfer Indicator
	last_xfr_lc1		: node;
	
	
	perr_vldR			: DFFE;		-- Parity Error Valid
	
	perr_oeR			: DFFE;		-- Parity Error Output Enable Regsiter
--	par_oeR				: DFFE;		-- Parity Output Enable Regsiter

	irdy_oeR			: DFFE;		-- Irdy Output Enable Regsiter
	ad_oeR				: DFFE;		-- AD Bus Output Enable Regsiter

--- Register-OR Optimization -------------------------------------------
%
	cbe_oeR_r1				: DFFE;		-- CBEN Bus Output Enable Regsiter
	cbe_oeR_r2				: DFFE;		-- CBEN Bus Output Enable Regsiter
	cbe_oeR_r1_d				: NODE;		-- CBEN Bus Output Enable Regsiter
	cbe_oeR_r2_d				: NODE;		-- CBEN Bus Output Enable Regsiter
	cbe_oeR_r2_d_lcell			: NODE;  -- added for hold time delay
--	cbe_oeR_d					: NODE;		-- CBEN Bus Output Enable Regsiter
	cbe_oeR					: NODE;		-- CBEN Bus Output Enable RegsiteR
%
-------------------------------------------------------------------------
	cbe_oeR_not				: DFFE;
	cbe_oeR					: NODE;
	cbe_oeR_r1_d				: NODE;		-- CBEN Bus Output Enable Regsiter
	cbe_oeR_r1_lc1				: NODE;
	cbe_oeR_r1_lc2				: NODE;
	cbe_oeR_r2_d				: NODE;		-- CBEN Bus Output Enable Regsiter
	cbe_oeR_r2_lc1				: NODE;
	cbe_oeR_r3_d				: NODE;
	
	req_or				: DFFE;		-- Request Output regsiter
	
	req64_or_lc[6..1]	: LCELL;
	req64_or_lc3_1a		: NODE;
	req64_or_lc3_1b		: NODE;
	req64_or_lc3_1c		: NODE;
	req64_or_lc3_1d		: NODE;
	req64_or_lc2_1a		: NODE;
	req64_or_lc1_1a		: NODE;
	req64_or_lc1_1b		: NODE;
	req64_or_lc1_1c		: NODE;
	req64_or_lc1_1d		: NODE;	

	req64_or		: NODE;		-- Frame Output Register D Input	
	req64_or_not			: DFFE;		-- Request Output regsiter
	
	frame_or_lc[4..1]	: LCELL;
	frame_or_lc3_1a		: NODE;
	frame_or_lc3_1b		: NODE;
	frame_or_lc3_1c		: NODE;
	frame_or_lc3_1d		: NODE;
	frame_or_lc2_1a		: NODE;
	frame_or_lc1_1a		: NODE;
	ADR_ADR2			: DFFE;
	frame_or_lc1_1b		: NODE;
	frame_or_lc1_1c		: NODE;
	frame_or_lc1_1d		: NODE;	

	frame_or	: NODE;		-- Frame Output Register D Input
	frame_or_not: DFFE;		-- Frame Output Register

--	MS_ADR2_d_lc		: NODE;
	
--	irdy_or_lc[5..1]	: node;
	irdy_or_lc[5..1]	: LCELL;
	irdy_or_lc1_1a		: NODE;				
	irdy_or_lc1_1b		: NODE;		
	irdy_or_lc1_1c		: NODE;	
	irdy_or_lc1_1d		: NODE;		
	irdy_or_lc1_1e		: NODE;		
	irdy_or_lc1_1f		: NODE;
	irdy_or_lc2_1a		: NODE;



	irdy_or			: NODE;			-- Irdy Output Register
	irdy_or_not		: DFFE;
	
--	lm_ack_or_lc[6..1]	: node;
--	lm_ack_or			: DFFE;-- Local Master Acknowledge Output Register


	lm_ack_or_r1		: DFFE;
	lm_ack_or_r2		: DFFE;
	lm_ack_or_r1_lc_1a	: node;
	lm_ack_or_r1_lc_1b	: node;
	lm_ack_or_r1_lc_1c	: node;
	lm_ack_or_r2_lc1	: node;
	lm_ack_or_r2_lc_1a	: node;
	lm_ack_or_r2_lc_1b	: node;
	lm_ack_or_r2_lc_1c	: node;
	lm_ack_or_r2_lc_1d	: node;					
	lm_ack_or_r2_lc_2a	: node;
	lm_ack_or_r2_lc_2b	: node;
	lm_ack_or_r2_lc_2c	: node;
	lm_ack_or_r2_lc_2d	: node;					
	lm_ack_or_r2_lc_3a	: node;
	lm_ack_or_r2_lc_3b	: node;
	lm_ack_or_r2_lc_3c	: node;					
	lm_ack_or_r2_lc_3d	: node;					
	lm_ack_or_r2_lc_3e	: node;
	lm_ack_or_r2_lc_3f	: node;
	lm_ack_or_r2_lc_4a	: node;	
	lm_ack_or_r2_lc_4b	: node;

	lm_ack_or_r3		: DFFE;
	lm_ack_or_r4		: DFFE;
	lm_ack_or			: NODE;-- Local Master Acknowledge Output Register


	lm_ldata_ack		: NODE;		-- Active High local data low acknowledge
	lm_hdata_ack		: NODE;		-- Active High local data high acknowledge
--	lm_ldata_ack_R		: DFFE;		-- Active High local data low acknowledge
--	lm_hdata_ack_R		: DFFE;		-- Active High local data high acknowledge

	lm_lack				: TFFE;		-- Toggle flop to determine which data is next
	64_trans			: SRFF;		-- 64 bit transaction
	
	
	trdy_det			: SRFF;
	retry_det			: SRFF;
	disc0_det			: SRFF;
	disc1_det			: SRFF;
	pxfr_det			: DFFE;
	
	perr_rep_setR		: DFFE;
	
	MS_TAR_R			: DFFE;		-- Registered MS_TAR signal
	
	stopR				: DFFE;		-- Registered Active High Stop Signal
	trdyR				: DFFE;		-- Registered Active High trdy Signal
	devselR				: DFFE;		-- Registered Active High devsel Signal
	ack64R				: DFFE;		-- Registered Active High ack64 Signal
	
	
	mstr_wr_dxfr		: node;		-- Master Write Data Transfer

IF (DUAL_ADDRESS_ENA == "NO") GENERATE
	ad_adr_sel			: node; 	-- Address Phase Select
END GENERATE;

	direct_xfr			: LCELL;--node;		-- Indicates pure 32->32 or 64->64 transfers
	pure_32				: SRFF;		-- Local and PCI 32 bit transfers

--	ms_adrR				: dffe;

	dati_hr_ena_lc		: NODE;

	adr2_ns				: dffe;
	ADR2n_ns			: dffe;
	WAIT_ndirect		: dffe;
	WAIT_ndirect_lc		: NODE;
	DXFR_write			: dffe;
	WAIT_WAIT32			: dffe;
	WAIT_WAIT32_lc1		: NODE;
	WAIT_WAIT32_lc2		: NODE;
	WAIT_WAIT32_lc3		: NODE;


	mstr_actv_lc		: NODE;
	ADOR_ena_lc : NODE;
	
BEGIN
	
--	ms_adrR.clk	= clk;
--	ms_adrR.clrn	= rstn;
--	ms_adrR.d		= MS_ADR;
--	ad_ir_ce_a	= ms_adrR;
	ad_ir_ce_a	= MS_ADR or MS_ADR2;	
--	cben_ir_ce_a	= ms_adrR;
	cben_ir_ce_a	= MS_ADR or MS_ADR2;	


	-- Registered Active high Stop Signal
	stopR.clk			= clk;
	stopR.clrn			= rstn;
	stopR.d				= stop;
		
	-- Registered Active high Ack64 Signal
	ack64R.clk			= clk;
	ack64R.clrn			= rstn;
	ack64R.d			= ack64;

	-- Registered Active high trdy Signal
	trdyR.clk			= clk;
	trdyR.clrn			= rstn;
	trdyR.d				= trdy;


	-- Registered Active high devsel Signal
	devselR.clk			= clk;
	devselR.clrn		= rstn;
	devselR.d			= devsel;
		

	junk =  junk 
		OR	MS_IDLE_d
		OR	MS_REQ_d
		OR	MS_ENA_d
		OR	MS_ADR_d
		OR	MS_PARK_d
		OR	MS_DXFR_d
		OR	MS_TAR_d	
		OR	MW_IDLE_d
		OR	MW_LXFR_d
		OR	MW_DXFR_d
		OR	MW_WAIT_d
		OR	MW_DXFR_32_d
		OR	MW_WAIT_32_d
		OR	MW_HOLD_d
		OR	MW_END_d
		OR	MW_LAST_d
		OR	MR_IDLE_d
		OR	MR_PXFR_d
		OR	MR_LPXFR_d
		OR	MR_DXFR_d
		OR	MR_LWAIT_d
		OR	MR_LLWAIT_d
		OR	MR_LLXFR_d
		OR	MR_END_d
		OR   mstr_done;

-- Local Side Input Registers

	
	lm_rdynR.clk		= clk;
	lm_rdynR.clrn		= rstn;
	lm_rdynR			= lm_rdyn;

	lm_req64R.clk		= clk;
	lm_req64R.clrn		= rstn;
	lm_req64R.s			= lm_req64;
	lm_req64R.r			= MS_TAR or MS_IDLE;

%
IF (DUAL_ADDRESS_ENA == "NO") GENERATE
	lm_adr64R.clk		= clk;
	lm_adr64R.clrn		= rstn;
	lm_adr64R.s			= gnd;
	lm_adr64R.r			= vcc;


ELSE GENERATE
	lm_adr64R.clk		= clk;
	lm_adr64R.clrn		= rstn;
	lm_adr64R.s			= lm_adr64;
	lm_adr64R.r			= MS_TAR or MS_IDLE;
END GENERATE;
%

--jot	lm_req32R.clk		= clk;
--jot	lm_req32R.clrn		= rstn;
--jot	lm_req32R.s			= lm_req32;
--jot	lm_req32R.r			= MS_TAR;

	
-- Main Master State machine	

IF (OPTIMIZE_MSTR == "NO") GENERATE

	Assert REPORT "NOT OPTIMIZING MASTER"
	Severity Warning;
	
	mstr_sm.clk			= clk;
	mstr_sm.reset		= not rstn;
	
	CASE mstr_sm IS
	
		-- Master IDLE 
		WHEN MS_IDLE	 =>	IF(mstr_ena and (lm_req64 # lm_req32) and lm_ackn) THEN
								mstr_sm 	= MS_REQ;
								MS_REQ_d	= VCC;
							ELSIF (park) THEN
								mstr_sm		= MS_PARK;
								MS_PARK_d	= VCC;