📄 pcic_m.tdf
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--
-- ***************** Version 18 *****************
-- User: Otan Date: 11/23/98 Time: 10:19a
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 17 *****************
-- User: Otan Date: 11/20/98 Time: 7:21p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 64-bit Target Read Debugging
--
-- ***************** Version 16 *****************
-- User: Otan Date: 11/20/98 Time: 4:20p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 64-bit Target Write and Memory Read works with simulation, local and
-- PCI wait states.
-- Added l_ldata_ackn and l_hdata_ackn to distinguish low and high dwords
-- for 32-bit PCI.
--
-- ***************** Version 14 *****************
-- User: Otan Date: 11/18/98 Time: 7:51p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read/Write works for single and burst cycles for PCI and local
-- wait states.
--
-- ***************** Version 12 *****************
-- User: Nprasad Date: 11/17/98 Time: 8:33p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added 64 bit place holders for all of the files. Completed par gen and
-- parity check for 64 bit.
--
-- ***************** Version 11 *****************
-- User: Nprasad Date: 11/16/98 Time: 10:05p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed Master Datapath to the top level. Added the extra signals
-- needed.
--
-- ***************** Version 10 *****************
-- User: Otan Date: 11/16/98 Time: 2:46p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read Implementation.
-- Changed lm_busyn -> not lm_rdyn.
-- Added the holding register.
--
-- ***************** Version 7 *****************
-- User: Otan Date: 11/14/98 Time: 1:12p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Read Successfully Simulated with Local and PCI wait states.
--
-- ***************** Version 6 *****************
-- User: Otan Date: 11/13/98 Time: 6:00p
-- Updated in $/MegaCore/HandOff/45/source/src
-- target read successfully simulated.
--
-- ***************** Version 5 *****************
-- User: Nprasad Date: 11/12/98 Time: 11:49p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed the output data path to the top level. Change the CE for the
-- input Ad registers so that data and command are till the next cycle.
-- Changed the Target local read state machine and the rest of the signals
-- to adjust for the change in the datapath. First draft for target local
-- read. Minor tweaks elsewhere.
--
-- ***************** Version 4 *****************
-- User: Nprasad Date: 11/11/98 Time: 10:28p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target local write data path complete. Target local write state machine
-- complete. Signals were modified to fucntion as specified. First draft.
--
-- ***************** Version 3 *****************
-- User: Nprasad Date: 11/11/98 Time: 7:11p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Address path has changed. Data path is through a partial change.
-- New signal names added. Other superficial changes.
--
-- ***************** Version 2 *****************
-- User: Nprasad Date: 10/26/98 Time: 11:37a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Removing PCI_b optimization
--
-- ***************** Version 1 *****************
-- User: Ziada Date: 10/22/98 Time: 4:34p
-- Created in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 32 *****************
-- User: Ziada Date: 9/25/98 Time: 5:27p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Updated perr_vld to perr_vldR
--
INCLUDE "maxplus2.inc";
PARAMETERS
(
OPTIMIZE_MSTR = "YES",
DUAL_ADDRESS_ENA = "YES"
);
SUBDESIGN 'pcic_m'
(
-- PCI Inputs
clk : INPUT; -- PCI Clock
rstn : INPUT; -- PCI Restet
gnt : INPUT; -- Active High PCI Grant Signal
frame : INPUT; -- Active High FRAMEn Input
irdy : INPUT; -- Active High IRDYn INPUT
trdy : INPUT; -- Active High TRDYn Input
devsel : INPUT; -- Active High DEVSELn Input
stop : INPUT; -- Active High STOPn Input
ack64 : INPUT; -- Active High Ack64n Input
perr : INPUT; -- Active high Parity Error
-- Configuration Space Inputs
mstr_ena : INPUT; -- Master Enable
lat_dat[7..0] : INPUT; -- Latency Timer Register Data
-- Local Side Inputs
lm_req32 : INPUT; -- Local Master 32 bit Request Signal
lm_req64 : INPUT; -- Local Master Request Signal
lm_last : INPUT; -- Local Master Last Transaction Signal
lm_rdyn : INPUT; -- Local Side Master Data Ready Input (1 cycle ahead)
low_lm_dati[31..0] : INPUT; -- Local Side Master Data Bus - Low
high_lm_dati[31..0] : INPUT; -- Local Side Master Data Bus - High
low_lm_beni[3..0] : INPUT; -- Local Side Master Byte Enables - Low
high_lm_beni[3..0] : INPUT; -- Local Side Master Byte Enables - High
--IF (DUAL_ADDRESS_ENA == "NO") GENERATE
-- lm_cmd[3..0] : INPUT; -- Local Side Master Command
-- lm_adri[31..0] : INPUT; -- Local Side Master Address Bus
--END GENERATE;
-- 64bit_PCI : INPUT; -- PCI bus consists of only 64 bit devices
-- lm_adr64 : INPUT = GND; -- Local Side 64-bit Addressing Request (Dual Address Cycle)
-- PCI Outputs
-- AD Bus Controls
low_data_out[31..0] : OUTPUT; -- Master Output Data to AD Output Register
high_data_out[31..0]: OUTPUT; -- Master Output Data to AD Output Register
ADOR_ena : OUTPUT; -- Master AD Output Registers clock Enable
ador_hi_dena : OUTPUT; -- Master AD Output Registers Disbale for 64 -> 32
hi_low_sel : OUTPUT; -- Master AD Output Select line to Select high data
ad_oe : OUTPUT; -- Master AD OE Output
ad_sel : OUTPUT; -- Master AD Output Mux Select
dati_HR_ena : OUTPUT; -- Master AD Hold Register Enable
hr_dat_sel : OUTPUT; -- Master AD Output Select line to chose the hold register data
ad_IR_ce_D : OUTPUT; -- AD Input Register Clock Enable Data
-- Command/byte enable Bus Signals
cbe_ce : OUTPUT; -- Command/Byte Enable Clock Enable Data
hr_cbe_sel : OUTPUT; -- Master CBE Output Select line to chose the hold register data
cbe_HR_ena : OUTPUT; -- Master CBE Hold Register Enable
low_cbe_out[3..0] : OUTPUT; -- Command/Byte Enable Output Registers - Low
high_cbe_out[3..0] : OUTPUT; -- Command/Byte Enable Output Registers - High
cbe_oe : OUTPUT; -- Command/Byte Enable Output Enable
-- Hand Shake Signals
frame_out : OUTPUT; -- FRAMEn Output Register
frame_oe : OUTPUT; -- Frame Output Enable
irdy_out : OUTPUT; -- IRDYn Output Register
irdy_oe : OUTPUT; -- IRDYn Output Enable
req64_out : OUTPUT; -- Req64n Output register
req64_oe : OUTPUT; -- Req64n Output Enable
req_out : OUTPUT; -- PCI Bus Request Output Register
-- Parity Signals
perr_vld : OUTPUT; -- Parity Error was detected
perr_oe : OUTPUT; -- PERR Output Enable
par_oe : OUTPUT; -- PAR Output Enable
-- Configuration Space Outputs
perr_rep_set : OUTPUT; -- PERR Reported Set
targ_abrt_set : OUTPUT; -- Set Command Register Target Abort Recieved Bit
mstr_abrt_set : OUTPUT; -- Set Command Regsiter Master Abort Recieved Bit
-- Local Side Outputs
lm_adr_ack : OUTPUT; -- local Master Address Acknowledge
lm_ackn : OUTPUT; -- PCI/B Ready/Acknowledge Signal
lm_ldata_ackn : OUTPUT; -- l_dato low is valid
lm_hdata_ackn : OUTPUT; -- l_dato high is valid
lm_dxfrn : OUTPUT; -- Local Master Data Transfer Signal
lm_tsr[9..0] : OUTPUT; -- Master Transaction Status Registers
-- 0: Master is requesting the Bus
-- 1: Master has been Granted the bus
-- 2: Master is in Address Phase
-- 3: Master is Transferring data
-- 4: Latency Timer has expired
-- 5: Master Recieved a retry
-- 6: Master Recieved a Disconnect with 0 Data Transfers
-- 7: Master Recieved a Disconnect with 1 Data Transfers
-- 8: PCI Data Transfer has occurred.
-- 9: 64 bit transaction
mstr_actv : OUTPUT; -- Master Active. Asserted while
-- mstr has ownership of bus.
mstr_wr_dxfr : OUTPUT; -- Master Write Data Transfer
hr_adr_sel : OUTPUT; -- Holding Register Select
64_trans_out : OUTPUT;
ad_ir_ce_a : OUTPUT;
cben_ir_ce_a : OUTPUT;
cben_ir_ce_d : OUTPUT; -- for parity checker -- Oliver Tan -- msr64_io.scf
dac_decode_out : OUTPUT;
)
VARIABLE
junk : NODE; -- Junk Node to get rid of the unused nodes
IF (OPTIMIZE_MSTR == "NO") GENERATE
-- Master State Machine Nodes
mstr_sm : MACHINE with STATES (
MS_IDLE,
MS_REQ,
MS_ENA,
MS_ADR,
MS_ADR2,
MS_PARK,
MS_DXFR,
MS_TAR);
-- Master State Machine Next state Nodes
MS_IDLE_d,
MS_REQ_d,
MS_ENA_d,
MS_ADR_d,
MS_ADR2_d,
MS_PARK_d,
MS_DXFR_d,
MS_TAR_d : NODE;
-- Master Write State machine Declaration
mw_sm : MACHINE with STATES (
MW_IDLE,
MW_LXFR,
MW_DXFR,
MW_WAIT,
MW_LAST,
MW_HOLD,
MW_DXFR_32,
MW_WAIT_32,
MW_END);
-- Master write State machine Next State Nodes
MW_IDLE_d,
MW_LXFR_d,
MW_DXFR_d,
MW_WAIT_d,
MW_LAST_d,
MW_HOLD_d,
MW_DXFR_32_d,
MW_WAIT_32_d,
MW_END_d : NODE;
-- Master read State machine Declaration
mr_sm : MACHINE with STATES (
MR_IDLE,
MR_PXFR,
MR_DXFR,
MR_LPXFR,
MR_LWAIT,
MR_LLWAIT,
MR_LLXFR,
MR_END);
-- Master write State machine Next State Nodes
MR_IDLE_d,
MR_PXFR_d,
MR_DXFR_d,
MR_LPXFR_d,
MR_LWAIT_d,
MR_LLWAIT_d,
MR_LLXFR_d,
MR_END_d : NODE;
ELSE GENERATE
---------- Master State Machine -------------------------------------------------
MS_IDLE_not,
MS_REQ,
MS_ENA,
MS_ADR,
MS_ADR2,
MS_PARK,
MS_DXFR,
MS_TAR : DFFE;
MS_IDLE,
MS_IDLE_d,
MS_REQ_d,
MS_ENA_d,
MS_ADR_d,
MS_ADR2_d,
MS_PARK_d,
MS_DXFR_d,
MS_TAR_d : NODE;
MS_ENA_d_lc : NODE;
---------- Master Write State Machine -----------------------------------------
MW_IDLE_not,
-- MW_LXFR,
-- MW_DXFR,
MW_WAIT,
-- MW_LAST,
MW_HOLD,
-- MW_DXFR_32,
MW_WAIT_32 : DFFE;
-- MW_END : DFFE;
MW_IDLE,
MW_IDLE_d,
-- MW_LXFR_d,
-- MW_DXFR_d,
MW_WAIT_d,
-- MW_LAST_d,
MW_HOLD_d,
-- MW_DXFR_32_d,
MW_WAIT_32_d : NODE;
MW_WAIT_32_d_lc_1a : NODE;
MW_WAIT_32_d_lc_1b : NODE;
MW_WAIT_32_d_lc_1c : NODE;
MW_WAIT_32_d_lc_1d : NODE;
-- MW_END_d : NODE;
MW_WAIT_d_lc1 : NODE;
MW_WAIT_d_lc2 : NODE;
MW_LXFR_r1 : DFFE;
MW_LXFR_r2 : DFFE;
MW_LXFR : NODE;
MW_LXFR_r1_d : NODE;
MW_LXFR_r2_d : NODE;
MW_LXFR_d : NODE;
MW_END_r1 : DFFE;
MW_END_r2 : DFFE;
MW_END : NODE;
MW_END_r1_d : NODE;
MW_END_r2_d : NODE;
MW_END_d : NODE;
MW_DXFR_32_r1 : DFFE;
MW_DXFR_32_r2 : DFFE;
MW_DXFR_32 : NODE;
MW_DXFR_32_r1_d : NODE;
MW_DXFR_32_r2_d : NODE;
MW_DXFR_32_d : NODE;
MW_LAST_r1 : DFFE;
MW_LAST_r2 : DFFE;
MW_LAST_r3 : DFFE;
MW_LAST : NODE;
MW_LAST_r1_d : NODE;
MW_LAST_r2_d : NODE;
MW_LAST_r3_d : NODE;
MW_LAST_d : NODE;
MW_LAST_r1_lc1 : NODE;
-- MW_LAST_r1_lc2 : NODE;
MW_LAST_r2_lc1 : NODE;
MW_LAST_r2_lc2 : NODE;
MW_LAST_r2_lc3 : NODE;
MW_DXFR_r1 : DFFE;
MW_DXFR_r2 : DFFE;
MW_DXFR_r2_lc_1a : NODE;
MW_DXFR_r2_lc_1b : NODE;
MW_DXFR_r2_lc_1c : NODE;
MW_DXFR_r2_lc_1d : NODE;
MW_DXFR_r2_lc_1e : NODE;
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