pcic_c.tdf

Altera AHDL语言设计的PCI总线

	adr_phase			: INPUT;	-- High One Clock after Address Phase
	cfg_dat_vld			: INPUT;	-- Write Data from ad_IR into corresponding register
	serr_det	 		: INPUT;	-- Signaled SERR
	adr_dec_ena			: INPUT;	-- Enable Address Decode valid During Address Phase

--	perr_vld			: INPUT;	-- Data Parity Error detected
	tabrt_set			: INPUT;	-- Signaled Target Abort
	tabrt_rcvd_set		: INPUT;	-- Recieved Target Abort
	mabrt_set			: INPUT;	-- Recieved Master Abort
	bar_hit_rst			: INPUT;	-- Reset the bar Hit bit at end of PCI access
	perr_det_set		: INPUT;	-- Detected Parity Error
	perr_rep_set		: INPUT;	-- Data Parity Error Signaled

	dac_cfg				: INPUT;
	

	mem_bar_hit			: OUTPUT;	-- One Of Memory BAR has HIT
	io_bar_hit			: OUTPUT;	-- One of I/O BAR has Hit
	cfg_dat_out[31..0]	: OUTPUT; 	-- Read Configuration Data Output

	-- Command Register Local Side Outputs

	io_ena 			: OUTPUT;	-- I/O Space Enable
	mem_ena			: OUTPUT;	-- Memory Space Enable
	mstr_ena 			: OUTPUT;	-- Bus Master Enable
	mwi_ena 			: OUTPUT;	-- Memory Write and Invalidate Enable
	perr_ena 			: OUTPUT;	-- Pariy Error Response Enable 
	serr_ena 			: OUTPUT;	-- SERR Enable

	-- Status Register Local Side Outputs
	perr_rep			: OUTPUT;	-- Data Parity Error Signaled
	tabrt_sig			: OUTPUT;	-- Signaled Target Abort
	tabrt_rcvd			: OUTPUT;	-- Recieved Target Abort
	mabrt_rcvd			: OUTPUT;	-- Recieved Master Abort
	serr_sig			: OUTPUT;	-- Signaled SERR
	perr_det			: OUTPUT;	-- Detected Parity Error


	lat_dat[7..0]		: OUTPUT;	-- Latency Timer Register Data
	cache_dat[7..0]		: OUTPUT;	-- Cache Line Register Data
	base_hit[5..0]		: OUTPUT;	-- Base Address Register Comparison Outputs
	exp_rom_bar_hit		: OUTPUT;

	dac_out				: OUTPUT;
	
	-- Local Side Configuration Space Support
	
	lcfg_adr[7..0]			: INPUT = GND;		-- Local Configuration Address
	lcfg_ben[3..0]			: INPUT = GND;		-- Local Configuration Byte enables
	lcfg_dat_in[31..0]		: INPUT = GND;		-- Local Configuration Data Input Bus
	lcfg_adr_vld			: INPUT = GND;		-- Local Configuration Address Valid
	lcfg_dat_vld			: INPUT = GND;		-- Local Configuration data Valid
	lcfg_dat_out[31..0]		: OUTPUT;		-- Local Configuration Data Output
	
)

VARIABLE
	cfg_adr_dec_tmp_node[5..0] : NODE;  -- temporary holding nodes so the repeat clause below will work

	mem_bar_hit			: NODE;--LCELL;
--	io_bar_hit			: NODE;--LCELL;
	
-- Temporary Variables
-- Instantiate BAR R/W Registes and Address Comparators
	junk[31..0]			: NODE;			-- Node Added to prevent Meaning less Warnings



-- Repeat this section for each of the BARs
	

	IF (NUMBER_OF_BARS >= 1+0) GENERATE
		
		IF (BAR0_MEM_LOC < 2) GENERATE
			
				bar0_ena[3..0]							: NODE;			-- Bar0 Register Write Enable
				bar0_reg[31 .. BAR0_READ_ONLY_BITS]		: DFFE;			-- BAR0 R/W Registers 
				bar0_comp	: lpm_compare WITH (							-- BAR0 Address Comparator
								LPM_WIDTH = (32-BAR0_READ_ONLY_BITS), 
								LPM_REPRESENTATION = "UNSIGNED",
								CHAIN_SIZE = 4);

				IF (BAR0_READ_ONLY_BITS > 4) GENERATE		
				bar0_ro_bits[BAR0_READ_ONLY_BITS-1..4] 	: NODE;			-- BAR0 Read Only Bits			
				END GENERATE;

		ELSE GENERATE
--			ASSERT (BAR0_MEM_LOC < 2)
--			REPORT "NUMBER_OF_BARS Must Be Greater Than 1"
--			SEVERITY ERROR;
			IF (BAR0_READ_ONLY_BITS_32 < 32) GENERATE
	
				bar0_ena[3..0]							: NODE;			-- Bar0 Register Write Enable
				bar0_reg[31 .. BAR0_READ_ONLY_BITS]		: DFFE;			-- BAR0 R/W Registers 
				bar0_comp	: lpm_compare WITH (							-- BAR0 Address Comparator
								LPM_WIDTH = (32-BAR0_READ_ONLY_BITS), 
								LPM_REPRESENTATION = "UNSIGNED",
								CHAIN_SIZE = 4);

				IF (BAR0_READ_ONLY_BITS > 4) GENERATE		
				bar0_ro_bits[BAR0_READ_ONLY_BITS-1..4] 	: NODE;			-- BAR0 Read Only Bits			
				END GENERATE;


			ELSE GENERATE
	
				bar0_ro_bits[BAR0_READ_ONLY_BITS_32-1..4] 	: NODE;			-- BAR0 Read Only Bits
			END GENERATE;
		
		END GENERATE;		

	END GENERATE;

	IF (NUMBER_OF_BARS >= 1+1) GENERATE
	
		IF (BAR0_MEM_LOC < 2) GENERATE

			bar1_ena[3..0]							: NODE;			-- Bar1 Register Write Enable
			bar1_reg[31 .. BAR1_READ_ONLY_BITS]		: DFFE;			-- BAR1 R/W Registers 
			bar1_comp	: lpm_compare WITH (							-- BAR1 Address Comparator
									LPM_WIDTH = (32-BAR1_READ_ONLY_BITS), 
									LPM_REPRESENTATION = "UNSIGNED",
									CHAIN_SIZE = 4);

			IF (BAR1_READ_ONLY_BITS > 4) GENERATE		
				bar1_ro_bits[BAR1_READ_ONLY_BITS-1..4] 	: NODE;			-- BAR1 Read Only Bits
			END GENERATE;
			
		
		ELSE GENERATE	

			bar1_ena[3..0]							: NODE;			-- Bar1 Register Write Enable
--			bar1_reg[31 .. BAR1_READ_ONLY_BITS_0]	: DFFE;			-- BAR1 R/W Registers 
			bar1_reg[BAR1_READ_WRITE_BITS-1..0]	: DFFE;			-- BAR1 R/W Registers 
			bar1_comp	: lpm_compare WITH (							-- BAR1 Address Comparator
									LPM_WIDTH = (BAR1_READ_WRITE_BITS), 
									LPM_REPRESENTATION = "UNSIGNED",
									CHAIN_SIZE = 4);
			
			IF (BAR1_READ_ONLY_BITS_0 > 0) GENERATE
				bar1_ro_bits_upper[31..8] : NODE;
				bar1_ro_bits_lower[BAR1_READ_ONLY_BITS_0-1..0] : NODE;
			ELSE GENERATE
				bar1_ro_bits_upper[31..8] : NODE;
--				bar1_ro_bits[BAR1_READ_ONLY_BITS-1..0] : NODE;
			END GENERATE;


		END GENERATE;


	END GENERATE;


	IF (NUMBER_OF_BARS >= 1+2) GENERATE
	
		bar2_ena[3..0]								: NODE;			-- Bar2 Register Write Enable
		bar2_reg[31 .. BAR2_READ_ONLY_BITS]		: DFFE;			-- BAR2 R/W Registers 
		bar2_comp	: lpm_compare WITH (							-- BAR2 Address Comparator
							LPM_WIDTH = (32-BAR2_READ_ONLY_BITS), 
							LPM_REPRESENTATION = "UNSIGNED",
							CHAIN_SIZE = 4);
		IF (BAR2_READ_ONLY_BITS > 4) GENERATE
		
			bar2_ro_bits[BAR2_READ_ONLY_BITS-1..4] 	: NODE;			-- BAR2 Read Only Bits
			
		END GENERATE;

	END GENERATE;

	IF (NUMBER_OF_BARS >= 1+3) GENERATE
	
		bar3_ena[3..0]								: NODE;			-- Bar3 Register Write Enable
		bar3_reg[31 .. BAR3_READ_ONLY_BITS]		: DFFE;			-- BAR3 R/W Registers 
		bar3_comp	: lpm_compare WITH (							-- BAR3 Address Comparator
							LPM_WIDTH = (32-BAR3_READ_ONLY_BITS), 
							LPM_REPRESENTATION = "UNSIGNED",
							CHAIN_SIZE = 4);
		IF (BAR3_READ_ONLY_BITS > 4) GENERATE
		
			bar3_ro_bits[BAR3_READ_ONLY_BITS-1..4] 	: NODE;			-- BAR3 Read Only Bits
			
		END GENERATE;
			
	END GENERATE;

	IF (NUMBER_OF_BARS >= 1+4) GENERATE
	
		bar4_ena[3..0]								: NODE;			-- Bar4 Register Write Enable
		bar4_reg[31 .. BAR4_READ_ONLY_BITS]		: DFFE;			-- BAR4 R/W Registers 
		bar4_comp	: lpm_compare WITH (							-- BAR4 Address Comparator
							LPM_WIDTH = (32-BAR4_READ_ONLY_BITS), 
							LPM_REPRESENTATION = "UNSIGNED",
							CHAIN_SIZE = 4);
		IF (BAR4_READ_ONLY_BITS > 4) GENERATE
		
			bar4_ro_bits[BAR4_READ_ONLY_BITS-1..4] 	: NODE;			-- BAR4 Read Only Bits
			
		END GENERATE;
			
	END GENERATE;

	IF (NUMBER_OF_BARS >= 1+5) GENERATE
	
		bar5_ena[3..0]								: NODE;			-- Bar5 Register Write Enable
		bar5_reg[31 .. BAR5_READ_ONLY_BITS]		: DFFE;			-- BAR5 R/W Registers 
		bar5_comp	: lpm_compare WITH (							-- BAR5 Address Comparator
							LPM_WIDTH = (32-BAR5_READ_ONLY_BITS), 
							LPM_REPRESENTATION = "UNSIGNED",
							CHAIN_SIZE = 4);
		IF (BAR5_READ_ONLY_BITS > 4) GENERATE
		
			bar5_ro_bits[BAR5_READ_ONLY_BITS-1..4] 	: NODE;			-- BAR5 Read Only Bits
			
		END GENERATE;

	END GENERATE;


	-- Expansion ROM Nodes
	IF (EXP_ROM_ENA == "YES") GENERATE
		exp_rom_comp	: lpm_compare With (
							LPM_WIDTH	= (32 - EXP_ROM_READ_ONLY_BITS),
							LPM_REPRESENTATION = "UNSIGNED",
							CHAIN_SIZE	= 4);
		
		exp_rom_hit		: NODE;
		exp_rom_hitR	: SRFF;
		
		exp_rom_ro_bits[EXP_ROM_READ_ONLY_BITS-1 .. 1] : NODE;
		
		IF (USE_EXP_ROM_DEFAULT == "NO") GENERATE
			exp_rom_reg[31.. EXP_ROM_READ_ONLY_BITS]	: DFFE;
			exp_rom_en[3..0]							: NODE;
			exp_rom_dec_ena								: DFFE;
		ELSE GENERATE
			exp_rom_temp_dat[31..0]						: NODE;
			exp_rom_reg[31.. EXP_ROM_READ_ONLY_BITS]	: NODE;
			exp_rom_en[3..0]							: NODE;
			exp_rom_dec_ena_not							: DFFE;
			exp_rom_dec_ena								: NODE;
		END GENERATE;

	END GENERATE;					

	exp_rom_access		: NODE;
	exp_rom_hit_lc1 : NODE;
	exp_rom_hit_lc2 : NODE;

	bar_selR[5..0]		: NODE;	-- Bar0 Register Select
	bar_hit_lc1			: NODE;
	bar_hit_lc2			: NODE;
	bar_hit_lc3			: NODE;
	bar[5..0][31..0] 	: NODE; 	-- Data for all Base Address Registers
	bar_hit[5..0]		: NODE;	-- Address = BAR Address
	bar_hitR[5..0]		: SRFF;	-- Registered bar_hit
	
	-- Instantite Configuration Address Decoder
	cfg_adr_dec			: pcic_cd ;		-- Config Address Space decoder
	
	dev_vend_selR				: NODE;	-- Device/Vendor ID Register Select				
	stat_cmd_selR				: NODE;	-- Status/Command Register Select
	class_rev_selR				: NODE;	-- Class Code/Revision ID Register Select
	bist_hdr_lat_cach_selR		: NODE;	-- BIST/Header Type/Latency Timer/Chache Line Register Select
	subs_subsvend_selR			: NODE;	-- Susystem ID/Subsystem Vendor ID Regsiter Select
	cap_ptr_selR				: NODE;	-- Capabilities Pointer Register Select
	exp_rom_selR				: NODE;	-- expansion ROM BAR Select
	lat_gnt_intpin_intln_selR	: NODE;	-- Max Latency/Min Grant/Interrupt Pin/Interrupt Line Regsiter Select

	-- Configuration Register Clock Enable active during Config Write Cycle
	stat_cmd_ena[3..0]			: NODE;	-- Status/Command Register Write Enable
	latency_cache_ena[1..0]		: NODE;	-- BIST/Header Type/Latency Timer/Chache Line Register Write Enable
	int_ln_ena0					: NODE;	-- Max Latency/Min Grant/Interrupt Pin/Interrupt Line  Write Enable
	
	cmd_reg[15..0]				: NODE;	-- Command Register Data

	stat_reg[15..0]				: NODE;	-- Status Register Data

	par_rep_rst					: NODE;	-- Reset Signaled Parity Error (Bit 24 Status/Command Register)
	targ_abrt_rst				: NODE;	-- Reset Signaled Target Abort (Bit 27 Status/Command Register)
	targ_abrt_rcvd_rst			: NODE;	-- Reset Received Target Abort (Bit 28 Status/Command Register)
	mstr_abrt_rst				: NODE;	-- Reset Recieved Master Abort (Bit 29 Status/Command Register)
	serr_rst					: NODE;	-- Reset Signaled SERR (Bit 30 Status/Command Register)
	perr_det_rst				: NODE;	-- Reset Detected Parity Error (Bit 31 Status/Command Register)

	lat_tmr_reg[4..0]			: DFFE;	-- Latency Timer Register Read/Write Bits
	lat_tmr[7..0]				: NODE;	-- Latency Timer Regsiter Read Only Bits

	cache_line[7..0]			: DFFE;	-- Cache Line Register
	int_ln_reg[7..0]			: DFFE;	-- Interrrupt Line Register
	
	config_data[31..0]			: NODE;	-- Configuration Data Mux Output
	ad_dat_out[31..0]			: DFFE;	-- AD Data Output Registers

	dev_vend_dat[31..0]			: NODE;	-- Device/Vendor ID Register Data
	stat_cmd_dat[31..0]			: NODE;	-- Status/Command Register Data
	class_revision_dat[31..0]		: NODE;	-- Class Code/Revision ID Register Data
	bist_hdr_ltncy_cach_dat[31..0]	: NODE;	-- BIST/Header Type/Latency Timer/Chache Line Register Data
	subs_subsvend_dat[31..0]		: NODE;	-- Susystem ID/Subsystem Vendor ID Regsiter Data
	cap_reg_dat[31..0]				: NODE;	-- Capabilities List pointer
	exp_rom_dat[31..0]				: NODE;	-- Expansion ROM BAR data
	lat_gnt_intpin_intln_dat[31..0]	: NODE;	-- Max Latency/Min Grant/Interrupt Pin/Interrupt Line Regsiter Data

	cap_ptr_dat[7..0]				: NODE;
	device_id_dat[15..0]			: NODE;	-- Device ID Register Data
	device_vend_id_dat[15..0]		: NODE;	-- Device Vendor ID Register Data
	class_dat[23..0]				: NODE;	-- Class Code Register Data
	rev_id_dat[7..0]				: NODE;	-- Revision ID Register Data
	subs_id_dat[15..0]				: NODE;	-- Subsystem ID Register Data
	subs_vend_id_dat[15..0]			: NODE;	-- Subsystem Vendor ID Register Data