📄 bsestart.lst
字号:
0000012c 00 398c 0000 362 la r12, 0(r12)
00000130 00 363
00000130 00 7d2c 4850 364 sub r9, r9, r12 # compute table size
00000134 00 7d29 1670 365 srawi r9, r9, 2 # in words
00000138 00 7d29 03a6 366 mtctr r9 # set up counter
0000013c 00 398c fffc 367 subi r12, r12, 4 # set up pointer to table
00000140 00 368
00000140 00 369 # program MCR with initial write command
00000140 00 3d20 0000 370 lis r9, MCR_UPMA_WRITE_INIT@h
00000144 00 6129 4000 371 ori r9, r9, MCR_UPMA_WRITE_INIT@l
00000148 00 372
00000148 00 373 UPMAInit:
00000148 00 850c 0004 374 lwzu r8, 4(r12) # get data from table
0000014c 00 9104 017c 375 stw r8, MDR(r4) # store data to MD register
00000150 00 9124 0168 376 stw r9, MCR(r4) # issue write command to MCR register
00000154 00 3929 0001 377 addi r9, r9, 1 # update UPMB address in write command
00000158 00 4200 fff0 378 bdnz UPMAInit
0000015c 00 379
0000015c 00 380 # Make SDRAM Ready
0000015c 00 381
0000015c 00 382 # Initialize Memory Periodic Timer Prescalar Register, MPTPR
0000015c 00 3980 0400 383 li r12, MPTPR_INIT
00000160 00 b184 017a 384 sth r12, MPTPR(r4)
00000164 00 385
00000164 00 386 # Initialize Machine A Mode Register, MAMR, 4 beats
00000164 00 3d80 d080 387 lis r12, MAMR_INIT@h
00000168 00 618c 2114 388 ori r12, r12, MAMR_INIT@l
0000016c 00 9184 0170 389 stw r12, MAMR(r4)
00000170 00 390
00000170 00 391 # Map CS2 to SDRAM
00000170 00 392
00000170 00 393
00000170 00 394 # program OR2
00000170 00 3d80 ff00 395 lis r12, CS_OR2_INIT@h
00000174 00 618c 0a00 396 ori r12, r12, CS_OR2_INIT@l
00000178 00 9184 0114 397 stw r12, CS_OR2(r4)
0000017c 00 398
0000017c 00 399
0000017c 00 400 # program BR2
0000017c 00 3d80 ff00 401 lis r12, CS_BR2_INIT@h
00000180 00 618c 0081 402 ori r12, r12, CS_BR2_INIT@l
00000184 00 9184 0110 403 stw r12, CS_BR2(r4)
00000188 00 404
00000188 00 405
00000188 00 406 # program MAR
00000188 00 3d80 0000 407 lis r12, MAR_UPMA_INIT@h
0000018c 00 618c 0088 408 ori r12, r12, MAR_UPMA_INIT@l
00000190 00 9184 0164 409 stw r12, MAR(r4)
00000194 00 410
00000194 00 411 # program MCR with setup
00000194 00 3d80 8000 412 lis r12, MCR_UPMA_SETUP_INIT@h
00000198 00 618c 4105 413 ori r12, r12, MCR_UPMA_SETUP_INIT@l
0000019c 00 414 # run setup
0000019c 00 9184 0168 415 stw r12, MCR(r4)
000001a0 00 416
000001a0 00 417 # program MCR with execute refresh
000001a0 00 3d80 8000 418 lis r12, MCR_UPMA_REFRESH_INIT@h
000001a4 00 618c 4830 419 ori r12, r12, MCR_UPMA_REFRESH_INIT@l
000001a8 00 420 # run refresh
000001a8 00 9184 0168 421 stw r12, MCR(r4)
000001ac 00 422
000001ac 00 423 # program MCR last
000001ac 00 3d80 8000 424 lis r12, MCR_UPMA_LAST_INIT@h
000001b0 00 618c 4106 425 ori r12, r12, MCR_UPMA_LAST_INIT@l
000001b4 00 426 # run last
000001b4 00 9184 0168 427 stw r12, MCR(r4)
000001b8 00 428
000001b8 00 429 #SDRAM is now ready to use
000001b8 00 430
000001b8 00 431 UPMBProgramEnd:
000001b8 00 432
000001b8 00 433 # End
000001b8 00 434
000001b8 00 435 CacheDisable:
000001b8 00 436 # Disable the instruction/data cache
000001b8 00 3d80 0400 437 lis r12, IC_DISABLE@h # load disable cmd
000001bc 00 618c 0000 438 ori r12, r12,IC_DISABLE@l
000001c0 00 4c00 012c 439 isync
000001c4 00 7d90 8ba6 440 mtspr IC_CST, r12 # disable I cache
000001c8 00 441
000001c8 00 3d80 0400 442 lis r12, DC_DISABLE@h # load disable cmd
000001cc 00 618c 0000 443 ori r12, r12, DC_DISABLE@l
000001d0 00 7c00 04ac 444 sync
000001d4 00 7d98 8ba6 445 mtspr DC_CST, r12 # disable D cache
000001d8 00 446
000001d8 00 447
000001d8 00 448 # initialize the stack pointer, just in case
000001d8 00 449 init_stack:
000001d8 00 3c20 0000 450 lis r1,__SP_INIT@h
000001dc 00 6021 0000 451 ori r1,r1,__SP_INIT@l
000001e0 00 3821 ffe0 452 addi r1,r1,-0x20
000001e4 00 453
000001e4 00 454
000001e4 00 455
000001e4 00 456 # END OF INITIALIZATION
000001e4 00 457 # GO TO bsecrt0.s
000001e4 00 458
000001e4 00 459
000001e4 00 460 ######### Test ############################
000001e4 00 461
000001e4 00 462 #bl SetLed
000001e4 00 463
000001e4 00 464 ######### End ############################
000001e4 00 465
000001e4 00 466
000001e4 00 467
000001e4 00 468
000001e4 00 4800 0000 469 b _start
000001e8 00 470
000001e8 00 471 # Should never get here, but in case we do...
000001e8 00 472 poststart:
000001e8 00 4800 0000 473 b poststart
000001ec 00 6000 0000 474 nop
000001f0 00 6000 0000 475 nop
000001f4 00 6000 0000 476 nop
000001f8 00 477
000001f8 00 478
000001f8 00 479 # UPMA setup for HHPPC860 16 MB SDRAM
000001f8 00 480 # for clocks 32-50 MHz
000001f8 00 481
000001f8 00 482 UPMATable_50:
000001f8 00 483 # single read. (offset 0x0 in UPM RAM)
000001f8 00 1f07 fc04 eeae 484 .long 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00
000001fe 00 fc04 11ad fc04
00000204 00 efbb bc00
00000208 00 1ff7 7c47 1ff7 485 .long 0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35
0000020e 00 7c35 efea bc34
00000214 00 1fb5 7c35
00000218 00 486 # burst read. (offset 0x8 in UPM RAM)
00000218 00 1f07 fc04 eeae 487 .long 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00
0000021e 00 fc04 10ad fc04
00000224 00 f0af fc00
00000228 00 f0af fc00 f1af 488 .long 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47
0000022e 00 fc00 efbb bc00
00000234 00 1ff7 7c47
00000238 00 ffff ffff ffff 489 .long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
0000023e 00 ffff ffff ffff
00000244 00 ffff ffff
00000248 00 ffff ffff ffff 490 .long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
0000024e 00 ffff ffff ffff
00000254 00 ffff ffff
00000258 00 491 # single write. (offset 0x18 in UPM RAM)
00000258 00 1f27 fc04 eeae 492 .long 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47
0000025e 00 bc00 01b9 3c04
00000264 00 1ff7 7c47
00000268 00 ffff ffff ffff 493 .long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
0000026e 00 ffff ffff ffff
00000274 00 ffff ffff
00000278 00 494 # burst write. (offset 0x20 in UPM RAM)
00000278 00 1f07 fc04 eeae 495 .long 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
0000027e 00 bc00 10ad 7c00
00000284 00 f0af fc00
00000288 00 f0af fc00 e1bb 496 .long 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff
0000028e 00 bc04 1ff7 7c47
00000294 00 ffff ffff
00000298 00 ffff ffff ffff 497 .long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
0000029e 00 ffff ffff ffff
000002a4 00 ffff ffff
000002a8 00 ffff ffff ffff 498 .long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
000002ae 00 ffff ffff ffff
000002b4 00 ffff ffff
000002b8 00 499 # refresh. (offset 0x30 in UPM RAM)
000002b8 00 1ff5 fc84 ffff 500 .long 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04
000002be 00 fc04 ffff fc04
000002c4 00 ffff fc04
000002c8 00 ffff fc84 ffff 501 .long 0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff
000002ce 00 fc07 ffff ffff
000002d4 00 ffff ffff
000002d8 00 ffff ffff ffff 502 .long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
000002de 00 ffff ffff ffff
000002e4 00 ffff ffff
000002e8 00 503 # exception. (offset 0x3c in UPM RAM)
000002e8 00 7fff fc07 ffff 504 .long 0x7ffffc07, 0xffffffff, 0xffffffff, 0xffffffff
000002ee 00 ffff ffff ffff
000002f4 00 ffff ffff
000002f8 00 505 #end of MPC823FADS UPMB programming
000002f8 00 506 UPMATable_50End:
000002f8 00 507
000002f8 00 508 .end
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -