📄 bsestart.lst
字号:
00001204 1d 181 .org (0x00001300)
00001300 20 4c00 0064 182 rfi
00001304 20 183 .org (0x00001400)
00001400 23 4c00 0064 184 rfi
00001404 23 185 .org (0x00001C00)
00001c00 26 4800 0000 186 b .
00001c04 26 187 .org (0x00001D00)
00001d00 29 4800 0000 188 b .
00001d04 29 189 .org (0x00001E00)
00001e00 2c 4800 0000 190 b .
00001e04 2c 191 .org (0x00001F00)
00001f00 2f 4800 0000 192 b .
00001f04 2f 193
00001f04 2f 194
00001f04 2f 195
00001f04 2f 196 ##################################
00001f04 2f 197 #
00001f04 2f 198 # START OF INITIALIZATION
00001f04 2f 199 #
00001f04 2f 200 ##################################
00001f04 2f 201
00001f04 2f 202 # Spotty chip initialization for the moment
00001f04 2f 203
00001f04 2f 204 # .org 0x40003000
00001f04 2f 205 # ASSIGNED BY LINKER COMMAND FILE
00001f04 2f 206
00001f04 2f 207 .text
00000000 00 208
00000000 00 209 bsestart:
00000000 00 210
00000000 00 211 ################################
00000000 00 212 #
00000000 00 213 # Init Temp Stack first
00000000 00 214 #
00000000 00 215 ################################
00000000 00 216
00000000 00 3c20 8000 217 lis r1, TEMP_STACK@h
00000004 00 6021 2ff0 218 ori r1, r1, TEMP_STACK@l
00000008 00 219
00000008 00 220 ################################
00000008 00 221
00000008 00 222
00000008 00 223
00000008 00 224 # Setup Unlock Key register r5: r5 is reserved from here to end of module
00000008 00 3ca0 55cc 225 lis r5, KEY_UNLOCK@h
0000000c 00 60a5 aa33 226 ori r5, r5, KEY_UNLOCK@l
00000010 00 227
00000010 00 228 SPR_Init:
00000010 00 229 # Initialize MSR and SRR1
00000010 00 3d80 0000 230 lis r12, MSR_INIT_NO_EE@h
00000014 00 618c 1042 231 ori r12, r12, MSR_INIT_NO_EE@l
00000018 00 7d80 0124 232 mtmsr r12
0000001c 00 7d9b 03a6 233 mtspr SRR1, r12
00000020 00 234
00000020 00 235 # Initialize Instruction Support Control Register
00000020 00 3d80 0000 236 lis r12, ICTRL_INIT@h
00000024 00 618c 0007 237 ori r12, r12, ICTRL_INIT@l
00000028 00 7d9e 23a6 238 mtspr ICTRL, r12
0000002c 00 239
0000002c 00 240 # Initialize Debug Enable Register
0000002c 00 3d80 fdc3 241 lis r12, DER_INIT@h
00000030 00 618c 400f 242 ori r12, r12, DER_INIT@l
00000034 00 7d95 23a6 243 mtspr DER, r12
00000038 00 244
00000038 00 245 # Initialize Decrementer Register
00000038 00 3d80 7fff 246 lis r12, DEC_INIT_MAX@h
0000003c 00 618c ffff 247 ori r12, r12, DEC_INIT_MAX@l
00000040 00 7d96 03a6 248 mtspr DEC, r12
00000044 00 249
00000044 00 250 # Initialize Interrupt Cause Register
00000044 00 251 # clear all interrupt causes by reading the ICR
00000044 00 7d94 22a6 252 mfspr r12, ICR
00000048 00 253
00000048 00 254 IMMR_Init:
00000048 00 255 # Initialize the IMMR register
00000048 00 256 # r4 is reserved from here to end of module
00000048 00 3c80 8000 257 lis r4, IMMR_INIT@h
0000004c 00 7c9e 9ba6 258 mtspr IMMR, r4 # initialize the IMMR register
00000050 00 7c9e 9aa6 259 mfspr r4, IMMR # read it back
00000054 00 5484 001e 260 rlwinm r4, r4, 0, 0, 15 # only high 16 bits count
00000058 00 261
00000058 00 262
00000058 00 263 ClockInit:
00000058 00 264 # Initialize System Clock Control Register
00000058 00 90a4 0380 265 stw r5, SCCRK(r4) # Unlock
0000005c 00 3d80 0100 266 lis r12, SCCR_INIT@h
00000060 00 618c 0000 267 ori r12, r12, SCCR_INIT@l
00000064 00 9184 0280 268 stw r12, SCCR(r4)
00000068 00 269
00000068 00 270 # Initialize the PLL, Low Power, and Reset Control Register
00000068 00 90a4 0384 271 stw r5, PLPRCRK(r4) # Unlock
0000006c 00 3d80 0090 272 lis r12, PLPRCR_INIT@h
00000070 00 618c c000 273 ori r12, r12, PLPRCR_INIT@l
00000074 00 9184 0284 274 stw r12, PLPRCR(r4)
00000078 00 275
00000078 00 276 SIU_Init:
00000078 00 277 # Initialize SIU Module Configuration Register
00000078 00 3d80 0001 278 lis r12, SIUMCR_INIT@h
0000007c 00 618c 2440 279 ori r12, r12, SIUMCR_INIT@l
00000080 00 9184 0000 280 stw r12, SIUMCR(r4)
00000084 00 281
00000084 00 282 # Initialize the System Protection Control Register
00000084 00 3d80 ffff 283 lis r12, SYPCR_INIT@h
00000088 00 618c ff88 284 ori r12, r12, SYPCR_INIT@l
0000008c 00 9184 0004 285 stw r12, SYPCR(r4)
00000090 00 286
00000090 00 287 SI_TimersInit:
00000090 00 288 # Initialize the Time Base Status and Control register
00000090 00 90a4 0300 289 stw r5, TBSCRK(r4) # Unlock
00000094 00 3980 00c3 290 li r12, TBSCR_INIT
00000098 00 b184 0200 291 sth r12, TBSCR(r4)
0000009c 00 292
0000009c 00 293 # Initialize Real Time Clock Register
0000009c 00 90a4 0324 294 stw r5, RTCK(r4) # Unlock
000000a0 00 3d80 0000 295 lis r12, RTC_INIT@h
000000a4 00 618c 0000 296 ori r12, r12, RTC_INIT@l
000000a8 00 9184 0224 297 stw r12, RTC(r4)
000000ac 00 298
000000ac 00 299 # Initialize Real Time Clock Status and Control Register
000000ac 00 90a4 0320 300 stw r5, RTCSCK(r4) # Unlock
000000b0 00 3980 00d3 301 li r12, RTCSC_INIT
000000b4 00 b184 0220 302 sth r12, RTCSC(r4)
000000b8 00 303
000000b8 00 304 # Initialize Real Time Clock Alarm Register
000000b8 00 90a4 032c 305 stw r5, RTCALK(r4) # Unlock
000000bc 00 3d80 ffff 306 lis r12, RTCAL_INIT@h
000000c0 00 618c ffff 307 ori r12, r12, RTCAL_INIT@l
000000c4 00 9184 022c 308 stw r12, RTCAL(r4)
000000c8 00 309
000000c8 00 310 # Initialize Real Time Clock Alarm Seconds Register
000000c8 00 90a4 0328 311 stw r5, RTSECK(r4) # Unlock
000000cc 00 3d80 ffff 312 lis r12, RTSEC_INIT@h
000000d0 00 618c ffff 313 ori r12, r12, RTSEC_INIT@l
000000d4 00 9184 0228 314 stw r12, RTSEC(r4)
000000d8 00 315
000000d8 00 316 # Check...
000000d8 00 8184 0228 317 lwz r12,RTSEC(r4)
000000dc 00 318
000000dc 00 319 # Initialize Periodic Interrupt Status and Control Register
000000dc 00 90a4 0340 320 stw r5, PISCRK(r4) # Unlock
000000e0 00 3980 0082 321 li r12, PISCR_INIT
000000e4 00 b184 0240 322 sth r12, PISCR(r4)
000000e8 00 323
000000e8 00 324
000000e8 00 325 MEMC_Init:
000000e8 00 326
000000e8 00 327
000000e8 00 328 # program BR0
000000e8 00 3d80 0000 329 lis r12, CS_BR0_INIT@h
000000ec 00 618c 0801 330 ori r12, r12, CS_BR0_INIT@l
000000f0 00 9184 0100 331 stw r12, CS_BR0(r4)
000000f4 00 332
000000f4 00 333 # program OR0
000000f4 00 3d20 ffe0 334 lis r9, CS_OR0_INIT@h
000000f8 00 6129 0160 335 ori r9, r9, CS_OR0_INIT@l
000000fc 00 9124 0104 336 stw r9, CS_OR0(r4)
00000100 00 337
00000100 00 338
00000100 00 339 # program OR1
00000100 00 3d20 ffe0 340 lis r9, CS_OR1_INIT@h
00000104 00 6129 0160 341 ori r9, r9, CS_OR1_INIT@l
00000108 00 9124 010c 342 stw r9, CS_OR1(r4)
0000010c 00 343
0000010c 00 344 # program BR1
0000010c 00 3d80 0020 345 lis r12, CS_BR1_INIT@h
00000110 00 618c 0801 346 ori r12, r12, CS_BR1_INIT@l
00000114 00 9184 0108 347 stw r12, CS_BR1(r4)
00000118 00 348
00000118 00 349
00000118 00 350 # Initialize UPMA (SDRAM)
00000118 00 351
00000118 00 352 UPMASetup:
00000118 00 353
00000118 00 354 # Set up for 50 MHz clock commands
00000118 00 355
00000118 00 3d80 0000 356 lis r12, UPMATable_50End@ha
0000011c 00 618c 0000 357 ori r12, r12, UPMATable_50End@l
00000120 00 392c 0000 358 la r9, 0(r12)
00000124 00 359
00000124 00 3d80 0000 360 lis r12, UPMATable_50@ha
00000128 00 618c 0000 361 ori r12, r12, UPMATable_50@l
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -