📄 bsestart.lst
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00000000 00 1 #
00000000 00 2 # bsestart.s
00000000 00 3 #
00000000 00 4 # Barnett Systems Engineering
00000000 00 5 # MPC823 Poweron Reset Initialization Assembly Source File
00000000 00 6 #
00000000 00 7 # Author: Harry E. Barnett 9/27/99
00000000 00 8 # harryb@hbbse.com http://www.hbbse.com
00000000 00 9 #
00000000 00 10 # Version V1.00
00000000 00 11 #
00000000 00 12 #########################################################################
00000000 00 13 .list
00000000 00 14 .file "bsestart.s"
00000000 00 15 .title "BSE MPC823 Poweron Reset Init Assembly Source File"
00000000 00 16
00000000 00 17 .text
00000000 00 18 .align 2
00000000 00 19
00000000 00 20 # PPC register equivalents
00000000 00 21 rTOC .equ 2
00000000 00 22 XRTOC .equ 20
00000000 00 23
00000000 00 24 # Memory Mapped Register Offsets
00000000 00 25
00000000 00 26 CS_BR0 .equ 0x100
00000000 00 27 CS_BR1 .equ 0x108
00000000 00 28 CS_BR2 .equ 0x110
00000000 00 29 CS_BR4 .equ 0x120
00000000 00 30 CS_OR0 .equ 0x104
00000000 00 31 CS_OR1 .equ 0x10C
00000000 00 32 CS_OR2 .equ 0x114
00000000 00 33 CS_OR4 .equ 0x124
00000000 00 34 MAMR .equ 0x170
00000000 00 35 MAR .equ 0x164
00000000 00 36 MBMR .equ 0x174
00000000 00 37 MCR .equ 0x168
00000000 00 38 MDR .equ 0x17C
00000000 00 39 MPTPR .equ 0x17A
00000000 00 40 PISCR .equ 0x240
00000000 00 41 PISCRK .equ 0x340
00000000 00 42 PLPRCR .equ 0x284
00000000 00 43 PLPRCRK .equ 0x384
00000000 00 44 RTC .equ 0x224
00000000 00 45 RTCAL .equ 0x22C
00000000 00 46 RTCALK .equ 0x32C
00000000 00 47 RTCK .equ 0x324
00000000 00 48 RTCSC .equ 0x220
00000000 00 49 RTCSCK .equ 0x320
00000000 00 50 RTSEC .equ 0x228
00000000 00 51 RTSECK .equ 0x328
00000000 00 52 SCCR .equ 0x280
00000000 00 53 SCCRK .equ 0x380
00000000 00 54 SIUMCR .equ 0x000
00000000 00 55 SYPCR .equ 0x004
00000000 00 56 TBSCR .equ 0x200
00000000 00 57 TBSCRK .equ 0x300
00000000 00 58
00000000 00 59 # Initializations
00000000 00 60
00000000 00 61 # SRN
00000000 00 62 # CS0,CS1 -> FLASH; CS2 -> SDRAM
00000000 00 63
00000000 00 64 #CS_BR0_INIT .equ 0x40000801
00000000 00 65 #CS_BR1_INIT .equ 0x40200801
00000000 00 66 #CS_BR2_INIT .equ 0x00000081
00000000 00 67 #CS_OR0_INIT .equ 0xFFE00160
00000000 00 68 #CS_OR1_INIT .equ 0xFFE00160
00000000 00 69 #CS_OR2_INIT .equ 0xFF000A00
00000000 00 70
00000000 00 71 CS_BR0_INIT .equ 0x00000801
00000000 00 72 CS_BR1_INIT .equ 0x00200801
00000000 00 73 CS_BR2_INIT .equ 0xff000081
00000000 00 74 CS_OR0_INIT .equ 0xFFE00160
00000000 00 75 CS_OR1_INIT .equ 0xFFE00160
00000000 00 76 CS_OR2_INIT .equ 0xFF000A00
00000000 00 77
00000000 00 78
00000000 00 79 DC_DISABLE .equ 0x04000000
00000000 00 80 DC_ENABLE .equ 0x02000000
00000000 00 81 DEC_INIT_MAX .equ 0x7FFFFFFF
00000000 00 82
00000000 00 83 # srn
00000000 00 84 # Change for New Vec location
00000000 00 85
00000000 00 86 MSR_INIT .equ 0x00009042
00000000 00 87 MSR_INIT_NO_EE .equ 0x00001042
00000000 00 88
00000000 00 89
00000000 00 90 DER_INIT .equ 0xFDC3400F
00000000 00 91
00000000 00 92 ICTRL_INIT .equ 0x00000007
00000000 00 93 IC_DISABLE .equ 0x04000000
00000000 00 94 IC_ENABLE .equ 0x02000000
00000000 00 95
00000000 00 96 IMMR_INIT .equ 0x80000000
00000000 00 97 TEMP_STACK .equ 0x80002ff0
00000000 00 98
00000000 00 99 KEY_UNLOCK .equ 0x55CCAA33
00000000 00 100
00000000 00 101 # srn 04.06.27
00000000 00 102 # SCCR.RTDIV=0, RT-clk divided by 4
00000000 00 103 # SCCR.RTSEL=0, select OSCM
00000000 00 104 SCCR_INIT .equ 0x01000000
00000000 00 105
00000000 00 106 # SRN
00000000 00 107 # INIT VALUE OF HHPPC'SDRAM (SEE mpc.init)
00000000 00 108
00000000 00 109 MAMR_INIT .equ 0xD0802114
00000000 00 110 MAR_UPMA_INIT .equ 0x00000088
00000000 00 111 MCR_UPMA_SETUP_INIT .equ 0x80004105
00000000 00 112 MCR_UPMA_REFRESH_INIT .equ 0x80004830
00000000 00 113 MCR_UPMA_LAST_INIT .equ 0x80004106
00000000 00 114 MCR_UPMA_WRITE_INIT .equ 0x00004000
00000000 00 115 MPTPR_INIT .equ 0x0400
00000000 00 116 PISCR_INIT .equ 0x0082
00000000 00 117
00000000 00 118 # srn 04.06.27
00000000 00 119 # GCLK = (9 + 1) * 5MHz = 50MHz
00000000 00 120 PLPRCR_INIT .equ 0x0090C000
00000000 00 121
00000000 00 122 RTCAL_INIT .equ 0xFFFFFFFF
00000000 00 123 RTCSC_INIT .equ 0x00D3
00000000 00 124 RTC_INIT .equ 0x00000000
00000000 00 125 RTSEC_INIT .equ 0xFFFFFFFF
00000000 00 126
00000000 00 127 SIUMCR_INIT .equ 0x00012440
00000000 00 128 SYPCR_INIT .equ 0xFFFFFF88
00000000 00 129 TBSCR_INIT .equ 0x00C3
00000000 00 130
00000000 00 131 # END OF DEFINE
00000000 00 132
00000000 00 133 # GLOBALS
00000000 00 134
00000000 00 135 .global poreset # start of system code
00000000 00 136 .extern DECIntr
00000000 00 137 .extern _start
00000000 00 138 .entry poreset
00000000 00 139 .text
00000000 00 140 .align 2
00000000 00 141
00000000 00 142 # SRN
00000000 00 143 # 07.23
00000000 00 144 #
00000000 00 145 # ADD FOR BURN FLASH
00000000 00 146
00000000 00 147 .org (0x00000000)
00000000 03 3230 3034 2e30 148 .string "2004.07.23"
00000006 03 372e 3233
0000000a 03 149
0000000a 03 150
0000000a 03 151
0000000a 03 152 # System Reset entry point: Offset 0x100
0000000a 03 153
0000000a 03 154 .org (0x00000100)
00000100 08 155 poreset:
00000100 08 4800 0000 156 b bsestart
00000104 08 157
00000104 08 158 # Decrementer exception entry point 0x900
00000104 08 159
00000104 08 160 .org (0x00000900)
00000900 0b 161 dec_exc:
00000900 0b 4800 0000 162 b DECIntr
00000904 0b 163
00000904 0b 164 # System Call exception entry point 0xC00
00000904 0b 165
00000904 0b 166 .org (0x00000C00)
00000c00 0e 167 sc_exc:
00000c00 0e 4800 0000 168 b OSCtxSw
00000c04 0e 169
00000c04 0e 170 .org (0x00000D00)
00000d00 11 171 trace_exc:
00000d00 11 4800 0000 172 b .
00000d04 11 173 .org (0x00000E00)
00000e00 14 4800 0000 174 b .
00000e04 14 175 .org (0x00001000)
00001000 17 4800 0000 176 b .
00001004 17 177 .org (0x00001100)
00001100 1a 4c00 0064 178 rfi
00001104 1a 179 .org (0x00001200)
00001200 1d 4c00 0064 180 rfi
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