📄 syslib.c
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/* sysLib.c - system-dependent library */
/* Copyright 1984-2001 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,24sep01,g_h move SIO, TIMER, EEPROM driver to be localy
01c,07may01,g_h add support for visionWARE 2.00
01d,21oct99,elk fixed system hang sysToMonitor() when using ^X to reboot
01c,19aug99,elk added local bus SDRAM and 4Mb/2Mb flash in sysPhysMemDesc.
01b,19apr99,elk added support for Ethernet.
01a,05mar99,elk adopted from estMDP8xx/sysLib.c
*/
#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "logLib.h"
#include "stdio.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/mmu603Lib.h"
#include "private/vmLibP.h"
#include "drv/mem/m8260Siu.h"
#include "drv/intrCtl/m8260IntrCtl.h"
#include "drv/parallel/m8260IOPort.h"
#include "m8260Pci.h"
#ifdef INCLUDE_REAL_TIME_CLOCK
#include "realClk.h"
#endif
/*add by yuecode*/
#include "flash.h"
#include "wrSbc8260.h"
/* Global data */
/*
* sysBatDesc[] is used to initialize the block address translation (BAT)
* registers within the PowerPC 603/604 MMU. BAT hits take precedence
* over Page Table Entry (PTE) hits and are faster. Overlap of memory
* coverage by BATs and PTEs is permitted in cases where either the IBATs
* or the DBATs do not provide the necessary mapping (PTEs apply to both
* instruction AND data space, without distinction).
*
* The primary means of memory control for VxWorks is the MMU PTE support
* provided by vmLib and cacheLib. Use of BAT registers will conflict
* with vmLib support. User's may use BAT registers for i/o mapping and
* other purposes but are cautioned that conflicts with caching and mapping
* through vmLib may arise. Be aware that memory spaces mapped through a BAT
* are not mapped by a PTE and any vmLib() or cacheLib() operations on such
* areas will not be effective, nor will they report any error conditions.
*
* Note: BAT registers CANNOT be disabled - they are always active.
* For example, setting them all to zero will yield four identical data
* and instruction memory spaces starting at local address zero, each 128KB
* in size, and each set as write-back and cache-enabled. Hence, the BAT regs
* MUST be configured carefully.
*
* With this in mind, it is recommended that the BAT registers be used
* to map LARGE memory areas external to the processor if possible.
* If not possible, map sections of high RAM and/or PROM space where
* fine grained control of memory access is not needed. This has the
* beneficial effects of reducing PTE table size (8 bytes per 4k page)
* and increasing the speed of access to the largest possible memory space.
* Use the PTE table only for memory which needs fine grained (4KB pages)
* control or which is too small to be mapped by the BAT regs.
*
* The BAT configuration for 4xx/6xx-based PPC boards is as follows:
* All BATs point to PROM/FLASH memory so that end customer may configure
* them as required.
*
* [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
*/
/*#define INCLUDE_LOCAL_BUS_SDRAM*/ /*hy add*/
UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
{
/* use IBAT0 to map flash execution space */
((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP),
((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT ),
/* Contrary to the misguided comments above, the other IBATS are being disabled here.... */
0, 0, /* I BAT 1 */
0, 0, /* I BAT 2 */
0, 0, /* I BAT 3 */
/* use DBAT0 to map flash into data space */
((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP),
((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT),
/* use DBAT1 to map CPM DPRAM and internal registers into data space */
/* NOTE! the internal space cannot be cached and should be guarded */
((INTERNAL_MEM_MAP_ADDR & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K | _MMU_UBAT_VS | _MMU_UBAT_VP),
((INTERNAL_MEM_MAP_ADDR & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),
/* use DBAT2 to map local bus SDRAM into data space -- if user wants it */
/* NOTE! the local bus SDRAM cannot be cached -- period */
0, 0, /* D BAT 2 */
/* Contrary to the misguided comments above, DBAT3 is being disabled here.... */
0, 0, /* D BAT 3 */
};
/*
* sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
* used by the MMU to translate addresses with single page (4k) granularity.
* PTE memory space should not, in general, overlap BAT memory space but
* may be allowed if only Data or Instruction access is mapped via BAT.
*
* PTEs are held, strangely enough, in a Page Table. Page Table sizes are
* integer powers of two based on amount of memory to be mapped and a
* minimum size of 64KB. The MINIMUM recommended Page Table sizes
* for 32-bit PowerPCs are:
*
* Total mapped memory Page Table size
* ------------------- ---------------
* 8 Meg 64 K
* 16 Meg 128 K
* 32 Meg 256 K
* 64 Meg 512 K
* 128 Meg 1 Meg
* . .
* . .
* . .
*
* [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
*/
PHYS_MEM_DESC sysPhysMemDesc [] =
{
/* The following maps the Vector Table and Interrupt Stack */
{
(void *) LOCAL_MEM_LOCAL_ADRS,
(void *) LOCAL_MEM_LOCAL_ADRS,
RAM_LOW_ADRS,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE | VM_STATE_MEM_COHERENCY
},
/* The following maps the Local SDRAM 64MB*/
{
(void *) RAM_LOW_ADRS,
(void *) RAM_LOW_ADRS,
LOCAL_MEM_SIZE - RAM_LOW_ADRS,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE | VM_STATE_MEM_COHERENCY
},
/* The following maps the FLASH on CS0 to its actual physical address and size */
{
(void *) CS0_FLASH_ADRS,
(void *) CS0_FLASH_ADRS,
CS0_FLASH_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
},
/* The following maps the flash on CS4, CS5 to its actual physical address and size */
{
(void *) FLASH_BASE_ADRS,
(void *) FLASH_BASE_ADRS,
FLASH_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
},
/* Remap */
{
(void *) 0x30000000,
(void *) 0x30000000,
0x2000000,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
} ,
{
(void *) 0x40000000,
(void *) 0x40000000,
0x2000000,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
}
};
int sysPhysMemDescNumEnt = NELEMENTS( sysPhysMemDesc ) ;
int sysBus = BUS ; /* system bus type (NONE) */
int sysCpu = CPU ; /* system CPU type (PPC8260) */
char *sysBootLine = BOOT_LINE_ADRS ; /* address of boot line */
char *sysExcMsg = EXC_MSG_ADRS ; /* catastrophic message area */
BOOL sysVmeEnable = FALSE ; /* by default no VME */
/* */
int sysProcNum ; /* processor number of this CPU */
int sysFlags ; /* boot flags */
char sysBootHost[ BOOT_FIELD_LEN ] ; /* name of host from which we booted */
char sysBootFile[ BOOT_FIELD_LEN ] ; /* name of file from which we booted */
/*IMPORT unsigned char glbEnetAddr [];*/
unsigned char glbEnetAddr [MAC_ADRS_LEN] = ETHERNET_MAC_ADRS; /*add by yuecode*/
/*
IMPORT unsigned char glbEnetAddr1[];
IMPORT unsigned char glbEnetAddr2 [];
*/
/* 8260 Reset Configuration Table (From page 9-2 in Rev0 of 8260 book) */
#define END_OF_TABLE 0
struct config_parms {
UINT32 inputFreq; /* MODCK_H */
UINT8 modck_h; /* | */
UINT8 modck13; /* |MODCK[1-3] */
UINT32 cpmFreq; /* Input | | CPM Core */
UINT32 coreFreq; /* | | | | | */
} modckH_modck13[] = {/* V V V V V */
{FREQ_33MHZ, 1, 0, FREQ_66MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 1, 1, FREQ_66MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 1, 2, FREQ_66MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 1, 3, FREQ_66MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 1, 4, FREQ_66MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 1, 5, FREQ_100MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 1, 6, FREQ_100MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 1, 7, FREQ_100MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 2, 0, FREQ_100MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 2, 1, FREQ_100MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 2, 2, FREQ_133MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 2, 3, FREQ_133MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 2, 4, FREQ_133MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 2, 5, FREQ_133MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 2, 6, FREQ_133MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 2, 7, FREQ_166MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 3, 0, FREQ_166MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 3, 1, FREQ_166MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 3, 2, FREQ_166MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 3, 3, FREQ_166MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 3, 4, FREQ_200MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 3, 5, FREQ_200MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 3, 6, FREQ_200MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 3, 7, FREQ_200MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 4, 0, FREQ_200MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 5, 5, FREQ_133MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 5, 6, FREQ_133MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 5, 7, FREQ_133MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 6, 0, FREQ_133MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 6, 1, FREQ_133MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 6, 2, FREQ_133MHZ, FREQ_300MHZ},
{FREQ_66MHZ, 6, 3, FREQ_166MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 6, 4, FREQ_166MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 6, 5, FREQ_166MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 6, 6, FREQ_166MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 6, 7, FREQ_166MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 7, 0, FREQ_166MHZ, FREQ_300MHZ},
{FREQ_66MHZ, 7, 1, FREQ_200MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 7, 2, FREQ_200MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 7, 3, FREQ_200MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 7, 4, FREQ_200MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 7, 5, FREQ_200MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 7, 6, FREQ_200MHZ, FREQ_300MHZ},
{FREQ_66MHZ, 7, 7, FREQ_233MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 8, 0, FREQ_233MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 8, 1, FREQ_233MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 8, 2, FREQ_233MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 8, 3, FREQ_233MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 8, 4, FREQ_233MHZ, FREQ_300MHZ},
{END_OF_TABLE,0,0,0,0}
};
/* Forward function references */
UINT32 vxImmrGet (void);
void vxImmrSet (UINT32 value);
void sysClkRateAdjust ( int * );
UINT32 sysChipRev(void);
void sysCpmReset(void);
UINT8 sysUserSwitchGet(void);
UINT32 sysCoreFreqGet(void);
UINT32 sysCpmFreqGet(void);
UINT32 sysInputFreqGet(void);
UINT8 sysModck13Get (void);
UINT8 sysModckHGet (void);
/* locals */
LOCAL UINT32 immrAddress = (UINT32) INTERNAL_MEM_MAP_ADDR;
/* Additional Components */
#if (NV_RAM_SIZE == NONE)
#include "mem/nullNvRam.c"
#else
/*#include "eeprom.c"*/ /*zsc move it*/
#include "mem/byteNvRam.c"
#endif
#ifdef INCLUDE_TFFS
#include "sysTffs.c"
#endif /* INCLUDE_TFFS */
#include "sys82xxDpramLib.c"
#include "sysSerial.c"
/*#include "sysSerialScc.c"*/
#include "m8260IntrCtl.c"
#include "m8260Timer.c"
/*#include "sysLed.c"*/
#include "sysIOPort.c"
#ifdef INCLUDE_CACHE_SUPPORT
#include "sysCacheLockLib.c"
#endif /* INCLUDE_CACHE_SUPPORT */
#ifdef INCLUDE_NETWORK
/*
#include "sysNet.h"
#include "sysNet.c"
*/ /*remove by yuecode*/
#ifdef INCLUDE_MOT_FCC
#include "sysMotFccEnd.c"
#endif /* INCLUDE_MOT_FCC */
/*
#ifdef INCLUDE_MOT_SCC
#include "sysMotSccEnd.c"
#endif
*/
/* INCLUDE_MOT_SCC */
#endif /* INCLUDE_NETWORK */
/*
#ifdef INCLUDE_VWARE_LAUNCH
#include "sysVware.c"
#endif
*/ /*yuecode*/
/* INCLUDE_VWARE_LAUNCH */
#ifdef INCLUDE_REAL_TIME_CLOCK
#include "realClk.c"
#endif
void RunLed(UINT8 mode)
{
UINT32 tmp = 0;
UINT8 how, t;
t = ((mode & 0x04) << 1) | ((mode & 0x08) >> 1)
| ((mode & 0x02) >> 1) | ((mode & 0x01) << 1) ;
how = (~t) & 0x0f;
tmp |= (how&0x0c) << 28;
tmp |= (how&0x03) << 8;
*(UINT32 *)(0x0f010d10) = tmp;
/*for(tmp = 0; tmp < 100000; tmp++);*/
}
/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/
char * sysModel( void )
{
return( "XPC8260 PowerQUICC II " ) ;
}
/*******************************************************************************
*
* sysBspRev - return the BSP version and revision number
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.1/0. BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/
char * sysBspRev( void )
{
return( BSP_VERSION BSP_REV );
}
/******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various feature of the EST MPC8260 board. It sets
* up the control registers, initializes various devices if they are present.
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