clib.h

Vxworks下的C例子程序

/* CLIB.h */
/* From: Darnold, Joel R <[e-mail]>   */
/* Definitions for Custom Laser Interface Board */
/******************************************************************************
*                                          LEDS
*      User I/O P5	  Programming P1    G  G  Y  R    Reset
*     -------------    -----------     -----------     ---
*    | o o o o o o1|  | o o o o o1|   |7O  O  O  O1|  | X |
*    | o o o o o o2|  | o o o o o2|   |8O  O  O  O2|  |   |
*     -------------    -----------     ------------    ---
*
*
*   Leds: Red 1 - EEPROM_CS
*         Red 2 - Error  (ERR)
*         Yel 3 - Fifo Full (FIFO_FULL)
*         Yel 4 - Fifo Empty (FIFO_EMPTY)
*         Grn 5 - Fifo Write Enable (FIFO_WREN_N)
*         Grn 6 - Fifo Output Enable (FIFO_OEN)
*         Grn 7 - 10MHz Clock Select (10MHz_SEL)
*         Grn 8 - Running (~1Hz)  (RUN)
*
*   P5: 1 -
*       2 - System tick
*
*	SW2 (Dip Switch): SW  Open      Closed
*                      1  Reticle   Wafer
*                      2  Stop      Run
*                      3            33MHz   3 & 4 Control the local PCI clock, 3 or 4
*                      4            10Mhz   must be closed but not both
*
******************************************************************************/

/*
#include "vxWorks.h"
#include "stdio.h"
#include "sysLib.h"
#include "math.h"
#include "drv/pci/pciLocalBus.h"
#include "drv/pci/pciIomapLib.h"
#include "fppLib.h"
#include "intLib.h"
#include "arch/ppc/ivPpc.h"
*/

#ifndef INCLUDE_MPIC  /* These are required for getting correct definitions from vm2600.h */
 #define INCLUDE_MPIC
#endif=20
#ifndef EXTENDED_VME
#define EXTENDED_VME
#endif
#include "c:/tornado/target/config/mv2304/mv2600.h"

#define PLX_VEN_ID	0x10b5
#define PCI9050_DEV_ID	0x9050

/* PLX 9050 Local Control Registers Address offsets */
#define LAS0RR	0x00
#define LAS1RR 	0x04
#define LAS2RR	0x08
#define LAS3RR 	0x0c
#define EROMRR	0x10
#define LAS0BA 	0x14
#define LAS1BA 	0x18
#define LAS2BA 	0x1c
#define LAS3BA 	0x20
#define EROMBA 	0x24
#define LAS0BRD	0x28
#define LAS1BRD	0x2c
#define LAS2BRD	0x30
#define LAS3BRD	0x34
#define EROMBRD	0x38
#define CS0BASE	0x3c
#define CS1BASE	0x40
#define CS2BASE	0x44
#define CS3BASE	0x48
#define INTCSR	0x4c
#define CNTRL	0x50

/* CLIB PCI Configuration information */

#define CLIB_PCI_DEVICE_ID	(((PCI9050_DEV_ID<<16)&0xffff0000) | PLX_VEN_ID) /* 0x905010b5 */ /* Used for pciFindDevice() */
#define CLIB_PMC_IO_SPACE	0x40100			/* CLIB Base for Local Control Registers in PCI I/O Space */
#define CLIB_PMC_MEM_SPACE	0x40000			/* CLIB Base for Local Control Registers in PCI Mem Space */
#define CLIB_PCI_IO0_ADRS	(PCI_IO_ADRS + CLIB_PMC_IO_SPACE) /* CPU address for Local Control Registers in PCI I/O Space */
#define CLIB_PCI_MEM0_ADRS	(PCI_MEM_ADRS + CLIB_PMC_MEM_SPACE)  /* CPU address for Local Control Registers in PCI MEM Space */
#define CLIB_PCI_FIFO_ADRS	(CLIB_PCI_MEM0_ADRS+0x100) /* PCI address of CLIB Fifo */
#define CLIB_PCI_ALTERA_ADRS	(CLIB_PCI_IO0_ADRS+0x100) /* PCI address if CLIB Altera registers */
#define CLIB_CPU_FIFO_ADRS	(CLIB_PCI_FIFO_ADRS) /* CPU address of CLIB Fifo */
#define CLIB_CPU_ALTERA_ADRS	(CLIB_PCI_ALTERA_ADRS) /* CPU address of CLIB Altera registers */

/* CLIB Altera register address offsets on local bus */

#define CLIB_CONTROL		0x00 	/* Register 0 */
#define CLIB_SAMP_MODULUS_LO	0x04	/* Register 1 */
#define CLIB_SAMP_MODULUS_HI	0x08	/* Register 2 */
#define CLIB_OVSAMP_MODULUS	0x0c	/* Register 3 */
#define CLIB_USER_IO_DIR	0x10	/* Register 4 */
#define CLIB_UNUSED		0x14	/* Register 5 */
#define CLIB_ERROR		0x18	/* Register 6 */
#define CLIB_STATUS		0x1c	/* Register 7 */


/* CLIB Alter register address on PCI bus */

#define CLIB_PCI_CONTROL		(CLIB_CONTROL + CLIB_PCI_ALTERA_ADRS)
#define CLIB_PCI_SAMP_MODULUS_LO	(CLIB_SAMP_MODULUS_LO + CLIB_PCI_ALTERA_ADRS)
#define CLIB_PCI_SAMP_MODULUS_HI	(CLIB_SAMP_MODULUS_HI + CLIB_PCI_ALTERA_ADRS)
#define CLIB_PCI_OVSAMP_MODULUS		(CLIB_OVSAMP_MODULUS + CLIB_PCI_ALTERA_ADRS)
#define CLIB_PCI_USER_IO_DIR		(CLIB_USER_IO_DIR + CLIB_PCI_ALTERA_ADRS)
#define CLIB_PCI_UNUSED			(CLIB_UNUSED + CLIB_PCI_ALTERA_ADRS)
#define CLIB_PCI_ERROR			(CLIB_ERROR + CLIB_PCI_ALTERA_ADRS)
#define CLIB_PCI_STATUS			(CLIB_STATUS + CLIB_PCI_ALTERA_ADRS)

/* CLIB Alter register address viewed from Processor */

#define CLIB_CPU_CONTROL		(CLIB_CONTROL + CLIB_CPU_ALTERA_ADRS)
#define CLIB_CPU_SAMP_MODULUS_LO	(CLIB_SAMP_MODULUS_LO + CLIB_CPU_ALTERA_ADRS)
#define CLIB_CPU_SAMP_MODULUS_HI	(CLIB_SAMP_MODULUS_HI + CLIB_CPU_ALTERA_ADRS)
#define CLIB_CPU_OVSAMP_MODULUS		(CLIB_OVSAMP_MODULUS + CLIB_CPU_ALTERA_ADRS)
#define CLIB_CPU_USER_IO_DIR		(CLIB_USER_IO_DIR + CLIB_CPU_ALTERA_ADRS)
#define CLIB_CPU_UNUSED			(CLIB_UNUSED + CLIB_CPU_ALTERA_ADRS)
#define CLIB_CPU_ERROR			(CLIB_ERROR + CLIB_CPU_ALTERA_ADRS)
#define CLIB_CPU_STATUS			(CLIB_STATUS + CLIB_CPU_ALTERA_ADRS)

/* CLIB register bit definitions */

/* CLIB_CONTROL register 0 */
#define CLIB_CTRL_SCLR_SAMPLE_CNT	0x01	/* 0=increment sample count for each control sample, 1=sample count stays zero , default=0 */
#define CLIB_IF_ENABLE			0x02	/* 0=interf. control signals (IF_AOH_N & IF_RDEN_N) disabled, 1=interf. interface enabled,default=0 */
#define CLIB_FIFO_ENABLE		0x04	/* 0=fifo control signal (F_WREN_N) disabled, 1=fifo interface enabled, default=0  */
#define CLIB_IF_POSN_RST_N		0x08	/* 0=all interf. position counters reset to 0,1=all counts show position, default=1  */
#define CLIB_TERM_ACCESS_EN		0x10 	/* 0=alter will only terminate local access that are addressed to CLIB, 1=terminate all local accesses, default=0 */
#define CLIB_REG_UNUSED			0x20
#define CLIB_MASTER			0x40	/* 0=slave mode, 1=master mode, default=1 */
#define CLIB_RUN			0x80 	/* 0=stop, 1=run, default=0 */

#define CLIB_CONTROL_RUN_MASTER_IF	(CLIB_IF_ENABLE|CLIB_FIFO_ENABLE|CLIB_IF_POSN_RST_N|CLIB_TERM_ACCESS_EN|CLIB_MASTER|CLIB_RUN)
#define CLIB_CONTROL_STOP_MASTER_IF	(CLIB_IF_ENABLE|CLIB_FIFO_ENABLE|CLIB_IF_POSN_RST_N|CLIB_TERM_ACCESS_EN|CLIB_MASTER)

#define CLIB_CONTROL_RUN_SLAVE_IF	(CLIB_IF_ENABLE|CLIB_FIFO_ENABLE|CLIB_IF_POSN_RST_N|CLIB_TERM_ACCESS_EN|CLIB_RUN)
#define CLIB_CONTROL_STOP_SLAVE_IF	(CLIB_IF_ENABLE|CLIB_FIFO_ENABLE|CLIB_IF_POSN_RST_N|CLIB_TERM_ACCESS_EN) 

/* CLIB_SAMP_MODULUS(s) Registers 1-3*/

/* The master CLIB clock is 10Mhz interf. clock, determine desired sample rate,
*  multiply this by number of oversamples + 1 (for servo sample), divide this
*  into 10MHz, this is value written into CLIB_SAMP_MODULUS(s)
*
*  Example
*	Desired servo rate = 7500Hz with 2 oversamples
*	2*7500 = 22500Hz,
*	100000000/22500 = 444.444
*	(int)444.444 = 0x01bc  (actual servo rate = 10Mhz/444 = 22.522kHz/3 = 7507.5Hz
*
*	write 0xbc to CLIB_CPU_SAMP_MODULUS_LO (lo byte of 0x01bc );
*	write 0x01 to CLIB_CPU_SAMP_MODULUS_HI (hi byte of 0x01bc );
*	write 0x02 to CLIB_CPU_OVSAMP_MODULUS  (meaning 2 oversamples)
*/

/* CLIB_USER_IO_DIR Register 4*/

#define CLIB_USER_IO1_DIR	0x01

/* CLIB_ERROR Register 6 */
/* A write to CLIB_ERROR clears the error register */
/* a 1 = error condition */
#define CLIB_FIFO_OEN_CONFLICT	0x01
#define CLIB_FIFO_FLAG_ERROR	0x02
#define CLIB_FIFO_FULL_ERROR	0x04
#define CLIB_TERM_ACCESS_ERROR	0x08
/* bits 4-7 are unused */

/* CLIB_STATUS Register 7 */
/* A write to CLIB_STATUS register clears local interrupt (LPCI_IRQ) */
#define CLIB_FIFO_EMPTY			0x01	/* 1=fifo is empty */
#define CLIB_FIFO_FULL			0x02 /* 1=fifo is full */
#define CLIB_IRQ_ASSERTED		0x04 /* 0=local interrupt is asserted */
#define CLIB_STATUS_UNUSED		0x08
#define CLIB_ALTERA_ERROR		0x10 /* the logical OR of all error register bits */
#define CLIB_10MHZ_SELECTED		0x20 /* 1=CLIB is using interferometer clock */
#define CLIB_MASTER_SELECTED		0x40 /* connected to register 0_6 (1=Master) */
#define CLIB_RUN_SELECTED		0x80 /* connected to register 0_7 (1=Run) */