📄 crt0.s
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lcd_start equ $01004000
MON_STACKTOP EQU $DDA ; best place for the stack
******************************************************************************
* Register for MC68EZ328
******************************************************************************
M328BASE equ $FFFFF000
; SIM28 System Configuration Registers
SCR equ (M328BASE+$000)
IDR equ (M328BASE+$004)
; Chip Select Registers
GRPBASEA equ (M328BASE+$100)
GRPBASEB equ (M328BASE+$102)
GRPBASEC equ (M328BASE+$104)
GRPBASED equ (M328BASE+$106)
CSA equ (M328BASE+$110)
CSB equ (M328BASE+$112)
CSC equ (M328BASE+$114)
CSD equ (M328BASE+$116)
CSCR equ (M328BASE+$10A)
DRAMCFG equ (M328BASE+$C00)
DRAMMC equ (M328BASE+$C00)
DRAMCTL equ (M328BASE+$C02)
DRAMC equ (M328BASE+$C02)
SDCTRL equ (M328BASE+$C04)
EMUCS equ (M328BASE+$118)
CSCTR equ (M328BASE+$150)
; PLL Registers
PLLCR equ (M328BASE+$200) ; Control Reg
PLLFSR equ (M328BASE+$202) ; Freq Select Reg
PLLTSR equ (M328BASE+$204) ; Test Reg
; Power Control Registers
PCTLR equ (M328BASE+$206) ; Control Reg
; Interrupt Registers
IVR equ (M328BASE+$300) ; Interrupt Vector Reg
ICR equ (M328BASE+$302) ; Interrupt Control Reg
IMR equ (M328BASE+$304) ; Interrupt Mask Reg
ISR equ (M328BASE+$30C) ; Interrupt Status Reg
IPR equ (M328BASE+$310) ; Interrupt Pending Reg
; PIO Registers
; Port A Registers
PADIR equ (M328BASE+$400) ; Direction Reg
PADATA equ (M328BASE+$401) ; Data Reg
PAPUEN equ (M328BASE+$402) ; Pullup Enable Reg
; Port B Registers
PBDIR equ (M328BASE+$408) ; Direction Reg
PBDATA equ (M328BASE+$409) ; Data Reg
PBPUEN equ (M328BASE+$40A) ; Pullup Enable Reg
PBSEL equ (M328BASE+$40B) ; Select Reg
; Port C Registers
PCDIR equ (M328BASE+$410) ; Direction Reg
PCDATA equ (M328BASE+$411) ; Data Reg
PCPDEN equ (M328BASE+$412) ; Pull-down Enable Reg
PCSEL equ (M328BASE+$413) ; Select Reg
; Port D Registers
PDDIR equ (M328BASE+$418) ; Direction Reg
PDDATA equ (M328BASE+$419) ; Data Reg
PDPUEN equ (M328BASE+$41A) ; Pullup Enable Reg
PDSEL equ (M328BASE+$41B) ; port D select
PDPOL equ (M328BASE+$41C) ; Polarity Reg
PDIRQEN equ (M328BASE+$41D) ; IRQ Enable Reg
PDKBEN equ (M328BASE+$41E) ; Keyboard Enable Reg
PDIRQEDGE equ (M328BASE+$41F) ; IRQ Edge Reg
; Port E Registers
PEDIR equ (M328BASE+$420) ; Direction Reg
PEDATA equ (M328BASE+$421) ; Data Reg
PEPUEN equ (M328BASE+$422) ; Pullup Enable Reg
PESEL equ (M328BASE+$423) ; Select Reg
; Port F Registers
PFDIR equ (M328BASE+$428) ; Direction Reg
PFDATA equ (M328BASE+$429) ; Data Reg
PFPUEN equ (M328BASE+$42A) ; Pullup Enable Reg
PFSEL equ (M328BASE+$42B) ; Select Reg
; Port G Registers
PGDIR equ (M328BASE+$430) ; Direction Reg
PGDATA equ (M328BASE+$431) ; Data Reg
PGPUEN equ (M328BASE+$432) ; Pullup Enable Reg
PGSEL equ (M328BASE+$433) ; Select Reg
PJDIR equ (M328BASE+$438)
PJDATA equ (M328BASE+$439) ; Date reg
PJPUEN equ (M328BASE+$43A)
PJSEL equ (M328BASE+$43B)
PKDIR equ (M328BASE+$440)
PKDATA equ (M328BASE+$441)
PKPUEN equ (M328BASE+$442)
PKSEL equ (M328BASE+$443) ; Select Reg
PMDIR equ (M328BASE+$448)
PMDATA equ (M328BASE+$449)
PMPUEN equ (M328BASE+$44A)
PMSEL equ (M328BASE+$44B) ; Select Reg
; PWM Registers
PWMC equ (M328BASE+$500) ; Control Reg
PWMS equ (M328BASE+$502) ; Sample Reg
PWMCNT equ (M328BASE+$504) ; Count Reg
; Timer Registers
; Timer 1 Registers
TCTL equ (M328BASE+$600) ; Control Reg
TPRER equ (M328BASE+$602) ; Prescalar Reg
TCMP equ (M328BASE+$604) ; Compare Reg
TCR equ (M328BASE+$606) ; Capture Reg
TCN equ (M328BASE+$608) ; Counter
TSTAT equ (M328BASE+$60A) ; Status Reg
; SPI Registers
SPIMDATA equ (M328BASE+$800) ; Control/Status Reg
SPIMCONT equ (M328BASE+$802) ; Data Reg
; UART Registers
USTCNT equ (M328BASE+$900) ; Status Control Reg
UBAUD equ (M328BASE+$902) ; Baud Control Reg
UARTRX equ (M328BASE+$904) ; Rx Reg
UARTTX equ (M328BASE+$906) ; Tx Reg
UARTMISC equ (M328BASE+$908) ; Misc Reg
UARTNIPR equ (M328BASE+$90A) ; None-Integer Prscaler reg
; LCDC Registers
LSSA equ (M328BASE+$A00) ; Screen Start Addr Reg
LVPW equ (M328BASE+$A05) ; Virtual Page Width Reg
LXMAX equ (M328BASE+$A08) ; Screen Width Reg
LYMAX equ (M328BASE+$A0A) ; Screen Height Reg
LCXP equ (M328BASE+$A18) ; Cursor X Position
LCYP equ (M328BASE+$A1A) ; Cursor Y Position
LCWCH equ (M328BASE+$A1C) ; Cursor Width & Height Reg
LBLKC equ (M328BASE+$A1F) ; Blink Control Reg
LPICF equ (M328BASE+$A20) ; Panel Interface Config Reg
LPOLCF equ (M328BASE+$A21) ; Polarity Config Reg
LACDRC equ (M328BASE+$A23) ; ACD (M) Rate Control Reg
LPXCD equ (M328BASE+$A25) ; Pixel Clock Divider Reg
LCKCON equ (M328BASE+$A27) ; Clocking Control Reg
LRRA equ (M328BASE+$A29) ; Refresh Rate Adjust reg
LPOSR equ (M328BASE+$A2D) ; Panning Offset Reg
LFRCM equ (M328BASE+$A31) ; Frame Rate Control Mod Reg
LGPMR equ (M328BASE+$A33) ; Gray Palette Mapping Reg
LPWM equ (M328BASE+$A36) ; contrast control Reg
; RTC Registers
RTCHMSR equ (M328BASE+$B00) ; Hrs Mins Secs Reg
RTCALM0R equ (M328BASE+$B04) ; Alarm Register
RTCDAY equ (M328BASE+$B08) ; RTC date reg
RTCWD equ (M328BASE+$B0A) ; RTC watch dog timer reg
RTCCTL equ (M328BASE+$B0C) ; Control Reg
RTCISR equ (M328BASE+$B0E) ; Interrupt Status Reg
RTCIENR equ (M328BASE+$B10) ; Interrupt Enable Reg
RSTPWCH equ (M328BASE+$B12) ; Stopwatch Minutes
;ICEM registers
ICEMACR equ (M328BASE+$D00)
ICEMAMR equ (M328BASE+$D04)
ICEMCCR equ (M328BASE+$D08)
ICEMCMR equ (M328BASE+$D0A)
ICEMCR equ (M328BASE+$D0C)
ICEMSR equ (M328BASE+$D0E)
;
; C program assembly startup for an embedded environment.
; -------------------------------------------------------
;
; Written by Tomas Evensen 1993-04-17.
; Copyright 1993 Diab Data AB.
;
PSECT
XDEF start
ALIGN 4
nop
start:
; initialize a5 to sdata (provided by linker)
; move.l #__SDA_BASE_,a5
RESET_HARD:
clr.l d0
clr.l d1
clr.l d2
clr.l d3
clr.l d4
clr.l d5
clr.l d6
clr.l d7
.xref _main
.xref __init_main
.Xref ___init
;jsr __init_main
jsr _init_main_guts
jsr ___init:
jsr _main
_exit:
bra _exit
; section .init$00,2,C ; Jeff Barth per Diab instructions 3/9/99
; XDEF ___init
; ALIGN 4
;___init:
; section .fini,2,C
; Return from __init
; rts
; XDEF ___fini
;___fini:
; section .eini,2,C
; Return from ___fini
; rts
;| runtime routines - integer arithmetic
;| all routines uses a0,a1,d0,d1
;|
;| 860919 teve
.text
.globl lmuld, ulmuld
.globl lmul, ulmul ;| old way
ulmul:
lmul:
movl 4(a7),d0
movl 8(a7),d0
ulmuld:
lmuld: ;| long mul (both signed & unsigned)
movl d2,a0 ;| ops in d0,d1 : result in d0
movl d0,d2
orl d1,d2
swap d2
movw d2,d2
bnes .L0 ;| branch if true long
mulu d1,d0 ;| fast if (0 <= d0,d1 <= 32767)
movl a0,d2
rts
.L0:
movl d0,d2
mulu d1,d2
movl d2,a1
movl d0,d2
swap d2
mulu d1,d2
swap d1
mulu d1,d0
addl d2,d0
swap d0
clrw d0
addl d0,a1
movl a1,d0
movl a0,d2
rts
;| runtime routines - integer arithmetic
;| all routines uses a0,a1,d0,d1
;|
;| 860919 teve
.text
.globl ulremd, uldivd, lremd, ldivd
.globl aulremd, auldivd, alremd, aldivd
.globl ulrem, uldiv, lrem, ldiv ;| old way
.globl aulrem, auldiv, alrem, aldiv
divl: ;| long unsigned div & rem : d1 op d2 -> d1:q d0:r
moveq #0,d0
notw d0 ;| d0 = 0x000FFFF
cmpl d0,d2
bhis .L1 ;| if d2 is long it's hard
cmpl d0,d1
bhis .L01 ;| if d1 is long it's not so hard
divu d2,d1 ;| both are short
swap d1
movw d1,d0 ;| rem -> d0
clrw d1
swap d1 ;| quo -> d1
rts
.L01: movw d1,a1 ;| long op short
clrw d1
swap d1
divu d2,d1
movl d1,d0
swap d1
movw a1,d0
divu d2,d0
movw d0,d1
clrw d0
swap d0
rts
.L1: movl d1,d0 ;| long op long
clrw d0
swap d0
swap d1
clrw d1
movl d2,a1
moveq #0xF,d2
.L2: addl d1,d1
addxl d0,d0
cmpl d0,a1
bhis .L3
subl a1,d0
addqw #1,d1
.L3: dbra d2,.L2
rts
ulrem:
movl 4(a7),d0
movl 8(a7),d1
ulremd: ;| unsigned rem d0,d1 -> d0
movl d2,a0
movl d0,d2 ;| see if short rem is possible
orl d1,d2
swap d2
movw d2,d2
bnes ulremns
ulrems:
divu d1,d0
clrw d0
swap d0
movl a0,d2
rts
ulremns:
movl d1,d2
movl d0,d1
jsr divl
movl a0,d2
rts
lrem:
movl 4(a7),d0
movl 8(a7),d1
lremd: ;| signed rem d0,d1 -> d0
movl d2,a0
movl d0,d2 ;| see if short rem is possible
orl d1,d2
swap d2
movw d2,d2
beqs ulrems ;| do short
movl d1,d2
bges .L4
negl d2
.L4: movl d0,d1
tstl d1
bges .L5
negl d1
jsr divl
negl d0
movl a0,d2
rts
.L5:
jsr divl
movl a0,d2
rts
uldiv:
movl 4(a7),d0
movl 8(a7),d1
uldivd: ;| unsigned div d0,d1 -> d0
movl d2,a0
movl d0,d2 ;| see if short div is possible
orl d1,d2
swap d2
movw d2,d2
bnes uldivns
uldivs:
divu d1,d0
swap d0
clrw d0
swap d0
movl a0,d2
rts
uldivns:
movl d1,d2
movl d0,d1
jsr divl
movl d1,d0
movl a0,d2
rts
ldiv:
movl 4(a7),d0
movl 8(a7),d1
ldivd: ;| signed div d0,d1 -> d0
movl d2,a0
movl d0,d2 ;| see if short div is possible
orl d1,d2
swap d2
movw d2,d2
beqs uldivs
movl d1,d2
bges .L6
negl d2
movl d0,d1
bges .L7
negl d1
bras .L8
.L6: movl d0,d1
bges .L8
negl d1
.L7: jsr divl
negl d1
movl d1,d0
movl a0,d2
rts
.L8: jsr divl
movl d1,d0
movl a0,d2
rts
aulrem:
movl 4(a7),a0
movl 8(a7),d0
aulremd: ;| unsigned rem (a0),d0 -> (a0),d0
movl d2,-(a7)
movl d0,d2
movl (a0),d1
jsr divl
movl d0,(a0)
movl (a7)+,d2
rts
auldiv:
movl 4(a7),a0
movl 8(a7),d0
auldivd: ;| unsigned div (a0),d0 -> (a0),d0
movl d2,-(a7)
movl d0,d2
movl (a0),d1
jsr divl
movl d1,d0
movl d0,(a0)
movl (a7)+,d2
rts
alrem:
movl 4(a7),a0
movl 8(a7),d0
alremd: ;| signed rem (a0),d0 -> (a0),d0
movl d2,-(a7)
movl d0,d2
bges .L14
negl d2
.L14: movl (a0),d1
tstl d1
bges .L15
negl d1
jsr divl
negl d0
movl d0,(a0)
movl (a7)+,d2
rts
.L15:
jsr divl
movl d0,(a0)
movl (a7)+,d2
rts
aldiv:
movl 4(a7),a0
movl 8(a7),d0
aldivd: ;| signed div (a0),d0 -> (a0),d0
movl d2,-(a7)
movl d0,d2
bges .L16
negl d2
movl (a0),d1
bges .L17
negl d1
bras .L18
.L16: movl (a0),d1
bges .L18
negl d1
.L17: jsr divl
negl d1
movl d1,d0
movl d0,(a0)
movl (a7)+,d2
rts
.L18: jsr divl
movl d1,d0
movl d0,(a0)
movl (a7)+,d2
rts
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