pcicfg.c

来自「PCI总线的驱动程序」· C语言 代码 · 共 1,656 行 · 第 1/5 页

                DEBUGMSG(ZONE_INIT, (L"PCIBUS!PCICfgBridge: IRQ returned from OAL is outside of range (0-254).  Ignoring.\r\n"));

                // No interrupts
                Irq = 0xFF;
            }
        }

        DEBUGMSG(ZONE_INIT, (L"RequestIrq(%d/%d/%d) returns %d\r\n", Bus, Device, Function, Irq));
        
        ((PPCI_INT)(&Reg))->InterruptLine = (BYTE)Irq;
        PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_INTERRUPT, Reg);       
    
        // Disable expansion ROM, prefetchable memory space, upper memory window
        PCIConfig_Write(Bus, Device, Function, PCIBRIDGE_ROM, 0x0);
        PCIConfig_Write(Bus, Device, Function, PCIBRIDGE_PREFETCHABLE, 0x0000FFF0);
        PCIConfig_Write(Bus, Device, Function, PCIBRIDGE_BASE_UPPER32, 0x0);
        PCIConfig_Write(Bus, Device, Function, PCIBRIDGE_LIMIT_UPPER32, 0x0);
        
        // Set bridge control register
        Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_INTERRUPT);
        Reg = (Reg & 0x0000FFFF) | Info.BridgeControl << 16;
        PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_INTERRUPT, Reg);
    }   
    
    // Set Latency register
    Info.Latency = (Info.Latency > 0) ? Info.Latency : pBusInfo->Latency;   // use global bus value if not defined for bridge
    if (Info.Latency) {
        // Reprogram only if non-zero
        Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_HEAD);
        Reg = (Reg & 0xFFFF00FF) | ((Info.Latency & 0xFF) << 8);
        PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_HEAD, Reg);
    }
    
    // Set the bus numbers & secondary latency
    // Need to set the subordinate bus as max for now, then write
    // actual number after found all downstream busses
    (*pSubordinateBus)++;
    Info.SecondaryLatency = (Info.SecondaryLatency > 0) ? Info.SecondaryLatency : pBusInfo->SecondaryLatency;   // use global bus value if not defined for bridge
    BusReg = PCIConfig_Read(Bus, Device, Function, PCIBRIDGE_BUS_NUMBER);
    ((PBRIDGE_BUS)(&BusReg))->PrimaryBusNumber = (BYTE)Bus;
    ((PBRIDGE_BUS)(&BusReg))->SecondaryBusNumber = (BYTE)(*pSubordinateBus);
    ((PBRIDGE_BUS)(&BusReg))->SubordinateBusNumber = 0xFF;
    if (Info.SecondaryLatency) ((PBRIDGE_BUS)(&BusReg))->SecondaryLatencyTimer = (BYTE)Info.SecondaryLatency;
    PCIConfig_Write(Bus, Device, Function, PCIBRIDGE_BUS_NUMBER, BusReg);
      
    SecondaryMemSize = 0;
    SecondaryIoSize = 0;

    // Call PCICfgBus recursively
    if (!PCICfgBus(pBusInfo, *pSubordinateBus, pSubordinateBus, &SecondaryMemSize, &SecondaryIoSize)) {
        return FALSE;
    }
     
    // Set the proper value for subordinate bus
    ((PBRIDGE_BUS)(&BusReg))->SubordinateBusNumber = (BYTE)(*pSubordinateBus);
    PCIConfig_Write(Bus, Device, Function, PCIBRIDGE_BUS_NUMBER, BusReg);

 
    // Round up space required by secondary bus to 1MB boundary and then
    // align to proper boundary after that
    SecondaryMemSize = (SecondaryMemSize + 0x000FFFFF) & 0xFFF00000;
    if (((SecondaryMemSize - 1) & (SecondaryMemSize)) != 0) {
        for (i = 31; i > 1; i--) {
            if (SecondaryMemSize & (1 << i)) {
                SecondaryMemSize = (1 << (i+1));
                break;
            }
        }
    }

    SecondaryIoSize = (SecondaryIoSize + 0x00000FFF) & 0xFFFFF000;
    if (((SecondaryIoSize - 1) & (SecondaryIoSize)) != 0) {
        for (i = 31; i > 1; i--) {
            if (SecondaryIoSize & (1 << i)) {
                SecondaryIoSize = (1 << (i+1));
                break;
            }
        }
    }

    DEBUGMSG(ZONE_INIT, (L"PCIBUS!PCICfgBridge(Bus %d, Device %d, Function %d): Saved MemSize: 0x%X, Calculated MemSize: 0x%X, Saved IoSize: 0x%X, Calculated IoSize: 0x%X\r\n",
        Bus, Device, Function, SavedMemSize, SecondaryMemSize, SavedIOSize, SecondaryIoSize));
        
    // Take maximum of saved resource size (if any) and calculated resource size
    // For CEPC platform, the registry could set NOCONFIG =1 because the BIOS configure the PCI-PCI bridge
    // and it is different from how we configured. So we can not touch the window if this flag is set.
    if (Info.Matched && !Info.Configure) { 
        SecondaryMemSize =  SavedMemSize;
        SecondaryIoSize =  SavedIOSize;
    }
    else {
        SecondaryMemSize = (SecondaryMemSize > SavedMemSize) ? SecondaryMemSize : SavedMemSize;
        SecondaryIoSize = (SecondaryIoSize > SavedIOSize) ? SecondaryIoSize : SavedIOSize;
    }
    
    DEBUGMSG(ZONE_INIT, (L"PCIBUS!PCICfgBridge-(Bus %d, Device %d, Function %d, SecBus %d, SubBus %d, MemSize 0x%X, IoSize 0x%X)\r\n",
        Bus, Device, Function, ((PBRIDGE_BUS)(&BusReg))->SecondaryBusNumber, *pSubordinateBus, SecondaryMemSize, SecondaryIoSize));

    // Add bridge resource requirements
    // NOTE: We don't support prefetchable memory yet
    if (SecondaryMemSize) {
        PPCI_RSRC Rsrc = PCIRsrc_New(Bus, Device, Function, 0, SavedMemBase, SecondaryMemSize, TRUE, ((PBRIDGE_BUS)(&BusReg))->SecondaryBusNumber, MemPlaced, NULL);
        
        if (!Rsrc) {
            DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgBridge: Failed local alloc of Rsrc\r\n"));
            return FALSE;
        }
        
        PCIRsrc_Add(g_MemHead, Rsrc);
    }

    if (SecondaryIoSize) {
        PPCI_RSRC Rsrc = PCIRsrc_New(Bus, Device, Function, 0, SavedIOBase, SecondaryIoSize, TRUE, ((PBRIDGE_BUS)(&BusReg))->SecondaryBusNumber, IOPlaced, NULL);
        
        if (!Rsrc) {
            DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgBridge: Failed local alloc of Rsrc\r\n"));
            return FALSE;
        }
        
        PCIRsrc_Add(g_IoHead, Rsrc);
    }
    
    *pMemSize += SecondaryMemSize;
    *pIoSize += SecondaryIoSize;

    // Write Command value and reset bridge status
    Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_COMMAND_STATUS);
    Reg &= 0x7;
    Reg |= 0xFFFF0000 | (Info.Command & 0x000003FF);
    PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_COMMAND_STATUS, Reg);

    return TRUE;

}


//
// Initialize and configure CardBus Bridge
//
// NOTE: We do not support CardBus, only the PCMCIA part of CardBus.  The memory and I/O base registers are programmed
// to not decode addresses.
//
static BOOL
PCICfgCardBusBridge(
    PPCI_DEV_INFO pBusInfo,
    ULONG Bus,
    ULONG Device,
    ULONG Function,
    PPCI_COMMON_CONFIG pCfg,
    PULONG pSubordinateBus,
    PULONG pMemSize,
    PULONG pIoSize
    )
{
    DWORD Reg;
    PCI_DEV_INFO Info;

    DEBUGMSG(ZONE_FUNCTION, (L"PCIBUS!PCICfgCardBusBridge+(Bus %d, Device %d, Function %d, Vendor ID 0x%X, Device ID 0x%X)\r\n",
        Bus, Device, Function, pCfg->VendorID, pCfg->DeviceID));

    // Initialize Info structure
    PCIInitInfo(pBusInfo->RegPath, Bus, Device, Function, pCfg, &Info);

    // Attempt to find match for this device in the registry and get info
    if (PCICfgFindMatch(&Info)) {
        Info.Matched = TRUE;

        if (!RegGetInfo(&Info)) {
            return FALSE;
        }

        if (!Info.Configure) {
            // If instructed not to configure, disable device and return
            DEBUGMSG(ZONE_WARNING, (L"PCIBUS!PCICfgCardBusBridge: Registry says don't configure this device\r\n"));

            if (pCfg->Command & (PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE | PCI_ENABLE_BUS_MASTER)) {
                PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_COMMAND_STATUS, 0xFFFF0000);
            }
            
            return TRUE;
        }

        // Make sure the sum of Base entries is less than or equal to 1
        if (Info.MemBase.Num + Info.IoBase.Num > PCI_TYPE2_ADDRESSES) {
            DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgCardBusBridge: The number of registry values '%s' and '%s' under '%s' must sum to be less than %d.\r\n",
                PCIBUS_MEMBASE_VALNAME, PCIBUS_IOBASE_VALNAME, Info.RegPath, PCI_TYPE2_ADDRESSES));

            return FALSE;
        }

        // Make sure the sum of Len entries is less than or equal to 1
        if (Info.MemLen.Num + Info.IoLen.Num > PCI_TYPE2_ADDRESSES) {
            DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgCardBusBridge: The number of registry values '%s' and '%s' under '%s' must sum to be less than %d.\r\n",
                PCIBUS_MEMLEN_VALNAME, PCIBUS_IOLEN_VALNAME, Info.RegPath, PCI_TYPE2_ADDRESSES));

            return FALSE;
        }
    }

    // If ConfigEntry defined, call it instead of CheckBARs
    if (Info.ConfigEntry) {
        DWORD Status;
        
        // Load driver Dll and obtain ConfigEntry function address
        if (!LoadConfigEntry(&Info)) {
            DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgCardBusBridge: Failed LoadConfigEntry call\r\n"));

            return FALSE;
        }

        Status = ((PFN_CONFIGENTRY)(Info.ConfigInfo->ConfigEntryFn))(PCIBUS_CONFIG_RSRC, &Info, g_MemHead, g_IoHead, pMemSize, pIoSize);
        
        if (Status != ERROR_SUCCESS) {
            if (Status == ERROR_NOT_SUPPORTED) {
                // ConfigEntry point doesn't support this type of call, so do it here
                // Read the base address registers to determine space to allocate
                if (!PCICfgCheckBARs(&Info, pMemSize, pIoSize)) {
                    DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgCardBusBridge: Failed PCICfgCheckBARs call\r\n"));
                    
                    return FALSE;
                }
            } else {
                DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgCardBusBridge: Failed %s:%s call\r\n", Info.DllName, Info.ConfigEntryName));

                return FALSE;
            }
        }
    } else {
        // Read the base address registers to determine space to allocate
        if (!PCICfgCheckBARs(&Info, pMemSize, pIoSize)) {
            DEBUGMSG(ZONE_ERROR, (L"PCIBUS!PCICfgCardBusBridge: Failed PCICfgCheckBARs call\r\n"));
            
            return FALSE;
        }
    }

    // If device not already placed, configure interrupt
    if (!(pCfg->Command & (PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE))) {
        DEVICE_LOCATION DevLoc;
        DWORD Irq = 0xFF;

        Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_INTERRUPT);
        
        if (((PPCI_INT)(&Reg))->InterruptLine==0xff || ((PPCI_INT)(&Reg))->InterruptLine==0) { // Not be configured
            // Fill in device location structure
            DevLoc.IfcType = PCIBus;
            DevLoc.BusNumber = Bus;
            DevLoc.LogicalLoc = (Bus << 16) | (Device << 8) | Function;
            DevLoc.Pin = ((PPCI_INT)(&Reg))->InterruptPin;
            
            if (DevLoc.Pin) {
                // Interrupts used, get IRQ from OAL
                if (!RequestIrq(&DevLoc, &Irq)) {
                    DEBUGMSG(ZONE_WARNING, (L"PCIBUS!PCICfgCardBusBridge: Get IRQ call failed.\r\n"));
                    // No Interrupt
                    Irq = 0xff;
                } 
                else if (Irq > 254) {
                    DEBUGMSG(ZONE_WARNING, (L"PCIBUS!PCICfgCardBusBridge: IRQ returned from OAL is outside of range (0-254).  Ignoring.\r\n"));
                    
                    // No interrupts
                    Irq = 0xFF;
                }
            }
            
            DEBUGMSG(ZONE_INIT, (L"RequestIrq(%d/%d/%d) returns %d\r\n", Bus, Device, Function, Irq));
            
            ((PPCI_INT)(&Reg))->InterruptLine = (BYTE)Irq;
            PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_INTERRUPT, Reg);   
        }
    }
    
    // Disable memory and I/O windows
    PCIConfig_Write(Bus, Device, Function, PCICARDBUS_MEMBASE0, 0xFFFFF000);
    PCIConfig_Write(Bus, Device, Function, PCICARDBUS_MEMLIMIT0, 0x0);
    PCIConfig_Write(Bus, Device, Function, PCICARDBUS_MEMBASE1, 0xFFFFF000);
    PCIConfig_Write(Bus, Device, Function, PCICARDBUS_MEMLIMIT1, 0x0);
    PCIConfig_Write(Bus, Device, Function, PCICARDBUS_IOBASE0, 0xFFFFFFFC);
    PCIConfig_Write(Bus, Device, Function, PCICARDBUS_IOLIMIT0, 0x0);
    PCIConfig_Write(Bus, Device, Function, PCICARDBUS_IOBASE1, 0xFFFFFFFC);
    PCIConfig_Write(Bus, Device, Function, PCICARDBUS_IOLIMIT1, 0x0);
    
    // Set bridge control register
    Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_INTERRUPT);
    Reg = (Reg & 0x0000FFFF) | Info.BridgeControl << 16;
    PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_INTERRUPT, Reg);

    // Set Latency register
    Info.Latency = (Info.Latency > 0) ? Info.Latency : pBusInfo->Latency;   // use global bus value if not defined for bridge
    if (Info.Latency) {
        // Reprogram only if non-zero
        Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_HEAD);
        Reg = (Reg & 0xFFFF00FF) | ((Info.Latency & 0xFF) << 8);
        PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_HEAD, Reg);
    }
    
    // Set the bus numbers & secondary (CardBus) latency
    // Assume There is no bridge type device attached the CardBus Bridge
    (*pSubordinateBus)++;
    Info.SecondaryLatency = (Info.SecondaryLatency > 0) ? Info.SecondaryLatency : pBusInfo->SecondaryLatency;   // use global bus value if not defined for bridge
    Reg = PCIConfig_Read(Bus, Device, Function, PCICARDBUS_BUS_NUMBER);
    ((PBRIDGE_BUS)(&Reg))->PrimaryBusNumber = (BYTE)Bus;
    ((PBRIDGE_BUS)(&Reg))->SecondaryBusNumber = (BYTE)(*pSubordinateBus);
    ((PBRIDGE_BUS)(&Reg))->SubordinateBusNumber = (BYTE)(*pSubordinateBus);
    if (Info.SecondaryLatency) ((PBRIDGE_BUS)(&Reg))->SecondaryLatencyTimer = (BYTE)Info.SecondaryLatency;
    PCIConfig_Write(Bus, Device, Function, PCICARDBUS_BUS_NUMBER, Reg);
    
    // Write command value and reset device status
    Reg = PCIConfig_Read(Bus, Device, Function, PCI_CONFIG_COMMAND_STATUS);
    Reg &= 0x7;
    Reg |= 0xFFFF0000 | (Info.Command & 0x000003FF);
    PCIConfig_Write(Bus, Device, Function, PCI_CONFIG_COMMAND_STATUS, Reg);

    DEBUGMSG(ZONE_FUNCTION, (L"PCIBUS!PCICfgCardBusBridge-\r\n"));
        
    return TRUE;
}


//
// Read and check Base Address Registers, calculate size and allocate resources
//
static BOOL
PCICfgCheckBARs(
    PPCI_DEV_INFO pInfo,
    PULONG pMemSize,
    PULONG pIoSize
    )
{
    DWORD NumberOfRegs;
    ULONG Offset;
    ULONG i;