startup.s

WinCE5.0部分核心源码

        //  1: virtual 0xFFFFD000 to kernel's data page (read-write)
        //      (s4) = PFN_INCR
        //
        li      v0,  2                  // load 2 into wired
        mtc0    v0, wired               // load 2 into wired
        li      v0, KPAGE_USER
        mtc0    v0, entryhi

        ori     v0, t4, 0x03 | PG_CACHE // valid, global, cached
        add     v1, v0, s4              // valid, global, cached (next page : always 4k)
        mtc0    v0, entrylo0            // even page info
        mtc0    v1, entrylo1            // odd page info
        mtc0    zero, index
        ssnop                           // super scalar core requires 4 integer
        ssnop                           //  instructions to guarantee a 2 cycle hazard
        ssnop
        ssnop
        tlbwi                           // write indexed entry
        nop
        nop
        
        li      v0, KData
        mtc0    v0, entryhi
        ori     v0, t4, 0x07 | PG_CACHE // valid, dirty, global, cached
        add     v1, v0, s4              // valid, dirty, global, cached (next page : always 4k)
        mtc0    v0, entrylo0            // even page info
        mtc0    v1, entrylo1            // odd page info
        li      v0, 1
        mtc0    v0, index               // index = 1
        ssnop                           // super scalar core requires 4 integer instructions
        ssnop                           //  to guarantee a 2 cycle hazard
        ssnop
        ssnop
        tlbwi                           // write indexed entry
        nop
        nop
        nop


        // we have wired TLB entries for KData, now we can start using it
        

        // Install TLBMiss handler
        li      a0, 0x0000
#if defined(NKPROF)
        la      a1, CeLogTLBMissHandler
        la      a2, CeLogTLBMissHandler_End
#else   
        la      a1, TLBMissHandler
        la      a2, TLBMissHandler_End
#endif  // NKPROF
        move    a3, s6
        jalfix(InstallHandler)

        // Install 64-bit TLBMiss handler
#ifdef MIPSIV
        li      a0, 0x0080
#ifdef NKPROF
        la      a1, CeLogTLBMissHandler
        la      a2, CeLogTLBMissHandler_End
#else
        la      a1, TLBMissHandler
        la      a2, TLBMissHandler_End
#endif  // NKPROF
        move    a3, zero
        jalfix(InstallHandler)
#endif  //  MIPSIV

        // Install General Exception handler
        li      a0, 0x0180
        la      a1, GeneralException
        la      a2, GeneralException_End
        move    a3, s6
        jalfix(InstallHandler)

        // Install CacheError handler
        li      a0, 0x0100
        la      a1, CacheErrorHandler
        la      a2, CacheErrorHandler_End
        move    a3, s6
        jalfix(InstallHandler)
        nop
        nop

        LIGHTS(t0,t1, 0xFC)

        // Switch execution and stack to cached, un-mapped region.
        la      t1, cached
        j       t1                      // jump to cached segment
        nop

cached: li      sp, KStack              // (sp) = 0xFFFFF???

        LIGHTS(t0,t1, ~1)
        
        // update CPU specific parameters
        // (s0) = MIPS16 support
        // (s1) = tiny page support (indidate R41XX cpu)
        // (s3) = PFN_SHIFT
        // (s4) = PFN_INCR
        li      t0, (VA_PAGE+1)
        sw      s3, PfnShift
        sw      s1, IsR41XX
        subu    t0, t0, s3              // (t0) == (VA_PAGE+1) - PFN_SHIFT
        sw      s0, MIPS16Sup
        sw      s4, PfnIncr
        sw      t0, TlbShift            // TlbShift = (VA_PAGE+1) - PFN_SHIFT

        lw      a0, pTOC
        jalfix(KernelRelocate)
        
        LIGHTS(t0,t1, ~2)


// Since the kernel can not manipulate the PSR with atomic instructions
// the MIPS kernel maintains a BasePSR value that can be manipulated
// atomically.  This value is then copied into the PSR register.  Note: 
// While the BasePSR value has a valid interrupt mask, it NEVER has the
// IE bit set! Enable the base PSR for operating system use.
// Until now, all exceptions were sent to the boot ROM.  The kernel is
// not initialized far enough to take the virtual memory exceptions with the 
// exception of statically mapped regions created with NKCreateStaticMapping().
// Clear the BEV bit so that all vectors are delivered to the kernel.

	sw	zero, BasePSR
        mtc0	zero, psr

        LIGHTS(t0,t1, ~4)
        
        mfc0    a0, prid                // (a0) = process ID information
        nop                             // 1 cycle hazard??
        
        jalfix(MIPSInit)                // MIPS general initialization

        LIGHTS(t0,t1, 0)
        
	jalfix(OEMInit)

// OEMInit updates the interrupt mask within the BasePSR.  Clear the
// interrupt mask to prevent interrupts from accidently being delivered
// during the kernel initialization.  Note: GetKHeap uses INTERRUPT_ON
// which actually sets IE, GetKHeap is called during KernelInit before
// the kernel is fully initialized.  Deliver interrupts only after the
// kernel is fully initialized.

        lw      t0, BasePSR
        nop
        li      s0, ( 0xff << PSR_INTMASK )
        and     s0, t0                      //  Locate enabled interrupts.
        xor     t0, s0                      //  Mask all interrupts.
        sw      t0, BasePSR

	jalfix(KernelFindMemory)

// Enable 64-bit instructions as appropriate, but keep interrupts disabled.

	li	s1, PSR_XX_C | PSR_FR_C | PSR_UX_C //  Enable 64-bit instructions.
        mtc0	s1, psr
	sw	s1, BasePSR

// Finish the kernel initialization.

	jalfix(KernelInit)

// Now it is finally time to enable interrupts.  The kernel is now fully
// initialized and can handle the device interrupts.

        or      s1, s0                  //  Update the interrupt mask.
	sw	s1, BasePSR
	ori	s1, ( 1 << PSR_IE )     //  Enable interrupts.
	mtc0	s1, psr
	nop

// Schedule the first thread.
	j	FirstSchedule
	nop
	.end	StartUp


//------------------------------------------------------------------------------
// InstallHandler(vector, handler start, handler end, fIsR41XX)
//
//  Install an exception handler by copying the code into memory at the
// exception vector location. This method requires that a handler fit in the
// space between its vector location and the next vector.
//
//  Entry   (a0) = vector address
//      (a1) = ptr to start of handler code
//      (a2) = ptr to end of handler code
//      (a3) = need nop at the beginning of handler?
//  Exit    none
//  Uses    t0-2
//
//------------------------------------------------------------------------------
LEAF_ENTRY(InstallHandler)

        .set noreorder
        lui     t0, 0xA000
        or      a0, t0                  // force into un-cached segment
                                        
        subu    t2, a2, a1              // (t2) = # of bytes to copy
        sltu    t1, t2, 0x81            // (t1) = 0 iff length > 0x80
        beq     zero, t1, 20f           // handler too large to copy
        nop                             
        or      a1, t0                  // force into un-cached segment
10:     lw      t0, (a1)                
        lw      t1, 4(a1)               
        sw      t0, (a0)                
        sw      t1, 4(a0)               
        subu    t2, 8                   // (t2) = remaining bytes copy count
        addu    a0, 8                   // (a0) = ptr to dest for next 8 bytes
        bgtz    t2, 10b                 
        addu    a1, 8                   // (a1) = ptr to src of next 8 bytes
        
        j       ra
        nop

        // The handler is more than 0x80 bytes, just install a jump to it instead
        // of copying the entire handler.

20:     
        beq     zero, a3, 30f
        nop
        // Install handler for R41XX
        sw      zero, 0(a0)
        sw      zero, 4(a0)
        srl     a2, a1, 16
        sh      a2, 8(a0)
        li      a2, 0x3c1a
        sh      a2, 10(a0)              // lui k0, [high 16 bits of address]
        sh      a1, 12(a0)

        li      a2, 0x375a
        sh      a2, 14(a0)              // ori k0, k0, [low 16 bits of address
        li      a2, 0x03400008
        sw      a2, 16(a0)              // j k0
        j       ra
        sw      zero, 20(a0)            // nop
30:
        // Install handler for R4300
        srl     a2, a1, 16
        sh      a2, 0(a0)
        li      a2, 0x3c1a
        sh      a2, 2(a0)               // lui k0, [high 16 bits of address]
        sh      a1, 4(a0)

        li      a2, 0x375a
        sh      a2, 6(a0)               // ori k0, k0, [low 16 bits of address
        li      a2, 0x03400008
        sw      a2, 8(a0)               // j k0
        j       ra
        sw      zero, 12(a0)            // nop

        .set reorder
        .end    InstallHandler